[test-triage] i2c_csr_bit_bash assertion failure `TxWriteStableBeforeHandshake_A`

[luismarques]

Hierarchy of regression failure

Block level

Failure Description

UVM_INFO @ 0 ps: reporter [RNTST] Running test i2c_base_test...
UVM_INFO @   5141628 ps: (dv_base_vseq.sv:182) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Running csr bit_bash vseq iteration 1/2.
UVM_INFO @ 397210254 ps: (dv_base_vseq.sv:182) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Running csr bit_bash vseq iteration 2/2.
"../src/lowrisc_ip_i2c_0.1/rtl/i2c_fifos.sv", 316: tb.dut.i2c_core.u_fifos.TxWriteStableBeforeHandshake_A: started at 669944951ps failed at 670011618ps
    Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 670011618 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 670011618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

I've checked a lot of commits and this error has existed for over a year (though sometimes you need other seeds to reproduce).

Steps to Reproduce

• GitHub Revision: 729449db11a7f153c2fbd62edb79a5d11d093e72
• dvsim invocation command to reproduce the failure: ./util/dvsim/dvsim.py hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_csr_bit_bash --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117 --fixed-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Tests with similar or related failures

No response

[a-will]

It's a CSR test exclusion that needs to happen. The bit bash test fills the FIFO and causes an overflow, leading to the assertion firing.

[hcallahan-lowrisc]

Fixed by #23865 Duplicate of #22853