Open amit-kumarh opened 1 month ago
This was an oversight, and it actually isn't a limitation of the SRAM itself. Instead, the TL-UL frontend is forbidding sub-word writes due to...
There is some downstream logic to check for issues, though, and this miss was deemed acceptable for A0 (not qualifying for ECO).
Write-only access is intentional, however, for compatibility with different tech libraries. True dual-port SRAMs aren't always supported, and the emulations often don't work well for modules with complex timing / CDC like this one.
Description
Non-word writes to the SPI Device SRAM cause a store fault. We can write unaligned data by manually masking the bits, but in the a0 revision, there doesn't appear to be read access to the egress buffer, so this would require maintaining a shadow copy of the SRAM. See the Rust code below for an example to reproduce.