About TOOL_SRCS_DIR environment setting

[islengxw]

Hi, when i run top_eargray prj with chip_sanity testcase. In the simulation step, it report not set TOOL_SRCS_DIR environment variable, then quit. This error message produced by opentitan/hw/dv/tools/vcs/vcs.tcl, then i grep the "TOOL_SRCS_DIR" in the root forlder, i guess simulation will mkdir this forlder and copy the tcl files in the /hw/dv/tools/vcs and excution. if {[info exists ::env(TOOL_SRCS_DIR)]} { set tool_srcs_dir "$::env(TOOL_SRCS_DIR)" } else { puts "ERROR: tool script run without TOOL_SRCS_DIR environment variable." quit } But the whole config flow is very unfamiliar for me. And i didn't find the information about this env variable in the documentation. So could anybody help me explain where to define this env variable? and what's it for?

[cindychip]

Hi islengxw,

Thank you for your quesiotn, and apologize on the documentation about dvsim, we are currently working on it. The tool_srcs_dir should be set in the common_project_cfg.hjson file automatically. In current flow I would not expect this error. May I know your run command?

Thanks, Cindy

[islengxw]

Hi islengxw,

Thank you for your quesiotn, and apologize on the documentation about dvsim, we are currently working on it. The tool_srcs_dir should be set in the common_project_cfg.hjson file automatically. In current flow I would not expect this error. May I know your run command?

Thanks, Cindy

Hi Cindy, Thanks for you reply, i appreciate it very much, i used find . -name "common_project_cfg.hjson" , i find two place about this file. /hw/vendor/lowrisc_ibex/dv/uvm/data and /hw/data i am not sure which common_project_cfg.hjson file was called. i guess this file calling failed. I will dig more. And which command do you mean? you mean the simulatiuon cmd? my simulation cmd is: Command: /home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default/simv +disable_assert_final_checks +UVM_NO_RELNOTES -licqueue -ucli -do /home/ubuntu/prj/opentitan/hw/dv/tools/vcs/vcs.tcl +ntb_random_seed=3520446802 +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_base_vseq -l /home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/chip_sanity/06.10.20_20.27.26/run.log

my run cmd is just 'make' in the /prj/opentitan/hw/top_earlgrey/dv/ folder.

my compile cmd is : Command: vcs +define+PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric -top tb -top xbar_main_bind \ +define+UVM +define+UVM_NO_DEPRECATED +define+UVM_REGEX_NO_DPI +define+UVM_REG_ADDR_WIDTH=32 \ +define+UVM_REG_DATA_WIDTH=32 +define+UVM_REG_BYTENABLE_WIDTH=4 -sverilog -full64 \ -licqueue -timescale=1ns/1ps -kdb -lca -ntb_opts uvm-1.2 -Mdir=/home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default/simv.csrc \ -l /home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default/build.log \ -o /home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default/simv \ -f /home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default/build/lowrisc_dv_chip_sim_0.1/sim-vcs/lowrisc_dv_chip_sim_0.1.scr \ +incdir+/home/ubuntu/prj/opentitan/hw/top_earlgrey/dv/scratch/top_earlgrey/default \ -debug_access+pp +warn=noUII-L +warn=SV-NFIVC -assert svaext -CFLAGS --std=c99 -LDFLAGS \ -Wl,--no-as-needed Thanks lengxw

[cindychip]

Hi Lengxw,

My apologize, we should really update our documents. Actually if you look into the folder call opentitan/util/dvsim, we are migrating to this new simulation tool.

So to run top_level code, you can try the following command:

1. go to folder opentitan/hw/top_earlgrey/dv
2. run command ../../../util/dvsim/dvsim.py chip_sim_cfg.hjson -i all_once
   • chip_sim_cfg.hjson is the config file that contains most of the build and run file options
   • -i option follows the specific test/regression sets you want to run. all_once means running all the test randomly once.
   • For more compile and run options, you can type ../../../util/dvsim/dvsim.py -h

To answer your question, we are using /hw/data/common_project_cfg.hjson. I am definitely not an expert in tooling... .but I hope that helps. Feel free to comment if you have any further question.

[islengxw]

Hi Cindy, Thanks for your answering, frankly speak, i am a pure HW verification guy, definitely not familiar with the hjson format file. I will keep learning your team excellent tooling. I am sure it will be very helpful if your team update the document about this part. Thanks for your sharing.

BR lengxw

[cindychip]

For hjson testplan, you can refer to : https://docs.opentitan.org/util/dvsim/testplanner/README/ Here is another doc about hjson format: https://docs.opentitan.org/doc/rm/hjson_usage_style/ We do not have any detailed doc about dvsim yet, but should be there soon.

Also if you are running top_level test, make sure you have installed sw testing as well (https://docs.opentitan.org/doc/ug/getting_started_sw/). Our top-level test includes C testing. If you simple want to test the dvsim tool, you can try some ip_level modules first. (uart, gpio, rv_timer, hmac, etc). Our current progress is shown in this regression dashboard. ( https://reports.opentitan.org/hw/top_earlgrey/dv/summary.html)

Again, feel free to let us know if you run into any issues. Thanks for trying OpenTitan DV :) Cindy

Cindy Chen

On Tue, Jun 16, 2020 at 10:10 PM islengxw notifications@github.com wrote:

Hi Cindy, Thanks for your answering, frankly speak, i am a pure HW verification guy, definitely not familiar with the hjson format file. I will keep learning your team excellent tooling. I am sure it will be very helpful if your team update the document about this part. Thanks for your sharing.

BR lengxw

— You are receiving this because you were assigned. Reply to this email directly, view it on GitHub https://github.com/lowRISC/opentitan/issues/2466#issuecomment-645154567, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACXPOOPDOVLGVASGU4VWQITRXBF6BANCNFSM4N3A4YPA .

[islengxw]

Hi Cindy, Thank your very much. :)