Closed JunminHe closed 2 years ago
Hi @JunminHe. Thanks for reaching out. The Genesys2 is not one of the boards we officially support. Though I personally think it would be a fun experience to try the port, I would strongly recommend starting with the Nexys Video if it suits your intended use case and budget. At the very least, starting with the supported board will give you some important intuition for using the system, to help you know what to expect in managing the port. (@tomroberts-lowrisc, could you comment on the status of I2C in top_earlgrey
for the Nexys board?)
You can also gain a lot of useful experience from doing HW/SW cosimulations with verilator. @cfrantz or @mcy, may have some advice on how to proceed with learning the I2C DIFs. Once you have some good intuition for the software interfaces, you will be much better prepared to troubleshoot any hurdles you may face trying to move to an actual FPGA.
Thank you, @martin-lueker, so much for your advice. Sorry for polluting the other issues.
We have ported opentitan to Genesys2, and would like to try out the I2C controller. I saw the DV status is not 100% passing yet. Is it ready for use?
I2C is not used in the hello_world example. Do you have any I2C example I could take a look to learn how to configure the codec registers?
I2C should be present in top_earlgrey for the NexysVideo board, but I don't think we have any example code that uses it unfortunately
Thank you for your reply, I will try the port .
Closing as resolved. Please reopen if you have any follow up questions. Thanks
Hello, I am trying to use the opentitan I2C IP to control an audio codec chip, ADAU1761, on Genesys 2. I have to configure some related registers as shown below. I have read the i2c.hjson, i2c.sv, dif_i2c.c, dif_i2c.h and etc., but I am still not sure how to use the dif_i2c functions for configuring the codec control registers.
Can you give me some tips or reference code of similar applications in the opentitan project? For example, I want to set the ADAU1761 control register R0 (address 0x4000) to 8’h07. The codec device address is 7’b0111011.
Additionally, how can I set the pins of SCL and SDA in the top level?
Thank you!