lowRISC style-guides issues

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lowRISC Style Guides

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Why is SV interface usage discouraged ?

#73 arnonsha closed 6 months ago
1
Fix typo in code example

#72 rswarbrick closed 6 months ago
0
typo in the **Suffixes**

#71 OlgaEsula closed 6 months ago
1
FSM must be implement with two process blocks

#70 danieldanino17 closed 7 months ago
1
Fix inconsistent use of simulation/synthesis mismatch

#69 rfdonnelly closed 7 months ago
1
Inconsistent use of "simulation-synthesis mismatch"

#68 rfdonnelly closed 7 months ago
1
Continuous assignment from argumentless functions

#67 sifferman opened 11 months ago
2
Functions should avoid non-local references

#66 sifferman closed 11 months ago
11
Plagarism of the Google Verilog Style Guide

#65 jonmayer closed 1 year ago
2
Stance on wand / wor?

#64 johnMamish closed 1 year ago
1
Parameter naming convention inconsistencies

#63 colluca opened 1 year ago
0
[SVA] Provide guidance on SVAs

#62 sriyerg closed 1 year ago
1
[dv] add `Wait And Non-Forever Loop` guidance

#61 weicaiyang closed 1 year ago
0
add a reference to sv-tests

#60 josuah closed 1 year ago
2
fix two guideline deviations in the examples

#59 josuah closed 1 year ago
0
Add guidelines for chip-level test forcing and probing

#58 weicaiyang closed 2 years ago
0
Discourage the use of hierarchical references in synthesiable RTL code

#57 vogelpi closed 2 years ago
1
Linting file for spyglass

#56 rahulraveendran15-coder opened 2 years ago
5
Guidance on whether to add space between SV keyword 'wait' and parenthesis

#55 sriyerg closed 1 year ago
3
Exemptions on 'spaces around keywords' rule

#54 sriyerg closed 3 years ago
1
[sv] How to format module instantiations that fit in a single line?

#53 imphil opened 3 years ago
5
Use of SystemVerilog Interfaces

#52 MikeOpenHWGroup opened 3 years ago
12
Fix example code

#51 imphil closed 3 years ago
0
Format module port expressions in tabular style

#50 imphil closed 3 years ago
6
Prefer SystemVerilog 2017 instead of 2012

#49 imphil closed 3 years ago
1
How to align named ports in module instantiations?

#48 imphil closed 3 years ago
17
[style] Align FSM examples with register naming rule

#47 msfschaffner closed 3 years ago
1
DV style guide: mention non-compliant usage of disable

#46 imphil opened 3 years ago
2
[dv style guide] More macro usage guidelines

#45 sriyerg closed 3 years ago
1
blocking assignment must be used for a clock divider

#44 hirooih opened 3 years ago
4
Prefer SystemVerilog-2017 instead of 2012

#43 hirooih closed 3 years ago
6
Clarification changes

#42 hirooih closed 3 years ago
3
Scope of this style guide and questions

#41 hirooih opened 3 years ago
3
[vsg] add guidance on closing braces

#40 sjgitty closed 3 years ago
0
[SV] Placement of closing parentheses in initializer lists

#39 imphil closed 3 years ago
3
[style] update logical context guidance

#38 sjgitty closed 4 years ago
1
[dv/style] Handling EOT with phase_ready_to_end

#37 udinator closed 4 years ago
5
Clarify the usage of `parameter` in packages

#36 vogelpi closed 4 years ago
1
[SystemVerilog] parameter vs. localparam in packages

#35 vogelpi closed 4 years ago
5
[dv style guide] More macro usage guidelines

#34 sriyerg closed 3 years ago
5
Copy-edit in DV styleguide (prefix -> suffix)

#33 rswarbrick closed 4 years ago
0
[doc] Three new optional styles added

#32 mwbranstad closed 4 years ago
7
Recommendations around xprop in simulations

#31 GregAC opened 4 years ago
11
[UVM:styleguide] best end of test practices

#30 rasmus-madsen closed 4 years ago
13
Add guidance on functions and tasks

#29 GregAC closed 4 years ago
5
Use of functions and automatic

#28 GregAC closed 4 years ago
6
Add further advice around Xs and assertion use

#27 GregAC closed 4 years ago
1
Correct typos in VerilogCodingStyle.md

#26 felixonmars closed 4 years ago
0
[VSG] update Verilog Coding Style guidance on constants

#25 sjgitty closed 4 years ago
3
[verilog stlye guidelines] parameters should be all caps

#24 mwbranstad closed 3 years ago
14