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https://lowenware.com/blog/osdev/aarch64-gic-and-timer-interrupt/ #8

Open utterances-bot opened 4 years ago

utterances-bot commented 4 years ago

AArch64 GIC and timer interrupt - Löwenware

https://lowenware.com/blog/osdev/aarch64-gic-and-timer-interrupt/

Shadlock0133 commented 4 years ago

For your asm! you probably want something like this:

asm!("mrs x1, CNTFRQ_EL0
    msr CNTP_TVAL_EL0, x1
    mov x0, 1
    msr CNTP_CTL_EL0, x0"
    :::"x0", "x1", "CNTP_TVAL_EL0", "CNTP_CTL_EL0"
);
voxelias commented 4 years ago

At the moment of writing, I was up for a proof-of-concept solution. Now I am working on some abstractions to access the registers safely. There is a nice crate already, but due to educational purposes I want to implement something own. It really helps to understand and feel the language.

klimchuk commented 1 year ago

What hardware this article inteded for? I'm testing on qemu with -machine raspi3b and all I did was:

    asm!("mrs x1, CNTFRQ_EL0");
    asm!("msr CNTP_TVAL_EL0, x1");
    // CNTP timer 2 - ARM timer
    // CNTV timer 8 - virtual timer
    // Already activated therefore (1 << 7) is not necessary
    ptr::write_volatile(0x4000_0040 as *mut u32, 2);
    asm!("mov x0, 1");
    asm!("msr CNTP_CTL_EL0, x0");

And timer fired IRQ but not every second, much more often than that. I did not touch GIC at all!