Closed lucask07 closed 2 years ago
Completed with commit 8bdb35db3676e57bc49cdc9641b6497677104a36. The FPGA counts conversion start pulses sent to the ADS8686 modulo 24. This information is sent in the DDR data stream so that ADS data can be associated with each channel in the sequencer.
The alignment is completed by separate_ads_sequence
within https://github.com/lucask07/covg_fpga/blob/daq_v2/python/analysis/adc_data.py#L272
The ADS8686 sequencer free runs at 1 MSPS. We need to implement a small module count of conversion starts in the FPGA that allows us to map each DDR reading to a specific ADS MUX channel within the sequencer sequence. The counter should only be reset when the ADS8686 is also reset.