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lucask07 / covg_fpga

FPGA and Python experiment code for the digital ion channel amplifier project.
GNU General Public License v3.0
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ADS8686 channel 'A', 'B' not synchronized #28

Closed lucask07 closed 1 year ago

lucask07 commented 2 years ago

The ADS8686 channel 'A', 'B' are stored into the DDR at different 'cycle_cnts'. This was causing slight errors in impedance analyzer measurements until I shifted the channel 'A' results one cycle.

Instead in the FPGA code, we should store 'A', 'B' results at the same cycle count so that there is no need to synchronize in software. (Unfortunately, this will require edits to the function to read .h5 files data_to_names and will make old .h5 files incompatible with newer .h5 files).

lucask07 commented 2 years ago

This is addressed and tested (fixed impedance analyzer issues) in the ads_sync branch.