WbSignal_converter: create 1 clock cycle pulse

[lucask07]

These two code blocks seem to be generating a pulse that is one clock cycle wide (startread) on the rising edge of int_o:

  always@(posedge clk /*or posedge int_o*/) begin
      if(int_o && !readmarker)begin
         startread <= 1'b1;
         readmarker <= 1'b1;
      end
      else if(!int_o)begin
          readmarker <= 1'b0;
      end
      /*else begin
         startread <= 1'b0; 
      end*/
  end

always@(negedge clk)begin
    if(startread)begin
        startread <= 1'b0;
    end
    else begin
        startread <= startread;
    end
end

A best practice "rule" relevant here is to not mix positive edge and negative edge clock triggers, particularly for flip-flops driving the same signal.

A better approach follows the answer from Dave Tweed in this StackExchange answer

So this issue is to change the creation of startread to use a 2-stage synchronizer.