Wb_SignalConverter: avoid reg initializations

[lucask07]

Lines 33 and 34 state:

reg startread = 1'b0;
reg readmarker = 1'b0;

This may work in simulation but is not necessarily synthesizable. In hardware (i.e. on the FPGA), if you desire a register to be initialized to a certain value a flip-flop with a reset is needed. However, in certain scenarios, a reset may not be needed if all the inputs that create this signal initialize to known values.

Action items for this issue:

1. See if this synthesizes onto the FPGA
2. Think through if it is necessary to initialize these regs
3. If it is not, necessary remove the initialize
4. If it is, consider how to add into a flip-flop with a reset

[lucask07]

Closing this since it seems like Xilinx FPGAs can have a default reset value (so this does work).