Closed lucask07 closed 2 years ago
A synchronous always block sensitivity list can have a clock or a clock and a reset. A third signal in the sensitivity list is not good practice.
//state register always@(posedge rst or posedge clk or posedge startread/*int_o*/)begin
This issue is to remove posedge startread from the sensitivity list
posedge startread
Either, move startread out of the sensitivity list and into the logic of the state register always block Or, move startread into the next state logic.
startread
A synchronous always block sensitivity list can have a clock or a clock and a reset. A third signal in the sensitivity list is not good practice.
This issue is to remove
posedge startreadfrom the sensitivity listEither, move
startreadout of the sensitivity list and into the logic of the state register always block Or, movestartreadinto the next state logic.