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lucullusTheOnly / TinyWire

Composite Master and Slave I2C library for Atmels ATTiny microcontrollers
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Missing start condition of first master write after slave read #3

Closed lucullusTheOnly closed 6 years ago

lucullusTheOnly commented 6 years ago

With the last commit, which included bus watching, simple bus arbitration and stop condition detection, I get the following error: When starting a master write with the library after a reset or a previous slave read (with simultaneous master/slave functionality) the library abort the communication with error code 3 (Missing start condition). This means, that is was not possible to generate a valid start condition on the bus. But if I start another master write, it works without flaws.

I am currently working, to fix this problem. I found out, that using USIDR = 0xFF; in the Twi_slave_init() function solves the problem for the reset. I'm doing the same in the Twi_master_init() function, but this doesn't solve the rest of the problem.

If anyone has an idea, how to solve this, I would be glad to here about it.

lucullusTheOnly commented 6 years ago

Ok, I now solved the problem. Most importantly I changed the order of setting USI registers and setting IO-Port registers in the Twi_master_init() function. Previously the IO-Settings (which came first in the code) were generating a short pulse on SDA, which confused the I2C logic.

I also found another problem in the Bus Watching, which I could fix. In the PinChangeInterrupt the code registered a Stop condition, before one occurred. Basically because it didn't check, if the levels of SDA and SCL were held for a sufficient time. The library now waits for about 7us in the ISR and checks the pins again. with this the code should reliably detect the stop conditions.