Multiple CPU cores should be able to read and write on the EasyNIC at the same time.
Ideally these cores should all share the same transmit/receive interface and efficiently distribute traffic using an algorithm implemented on the CPU. This will likely require some accommodations to be made in the transmit/receive interface to avoid expensive synchronization between the cores and possibly some special rules for memory alignment/arenas/etc as floated on #5.
(The alternative of having the NIC switch packets between multiple transmit/receive interfaces would be nice but it may be prohibitively complex to implement a sufficiently general dispatching mechanism. The trouble with features like RSS is that they only cover special cases of protocols and hashing rules and so on.)
Multiple CPU cores should be able to read and write on the EasyNIC at the same time.
Ideally these cores should all share the same transmit/receive interface and efficiently distribute traffic using an algorithm implemented on the CPU. This will likely require some accommodations to be made in the transmit/receive interface to avoid expensive synchronization between the cores and possibly some special rules for memory alignment/arenas/etc as floated on #5.
(The alternative of having the NIC switch packets between multiple transmit/receive interfaces would be nice but it may be prohibitively complex to implement a sufficiently general dispatching mechanism. The trouble with features like RSS is that they only cover special cases of protocols and hashing rules and so on.)