daveshah1
commented
5 years ago Some more thoughts on this.
- The -04 variant of the VSC8486 seems to have better publicly available docs, not fully sure of the differences. Still seems to work for the XGMII to XFI (i.e. SFP+) interface fine.
- I am assuming that the aim is SFP+ and not 10GbaseT...
- If no external memory is needed (and I don't think it is given the EasyNIC concept), then two ports should be just about doable on the biggest ECP5 packages. Max raw PCIe bandwidth is 20Gbps, ie 16Gbps after 8b10b, so 8Gbps per port which is probably usable?
lukego
MegabytePhreak
mslavescu
Suppose we wanted to build a 10G EasyNIC. Is there suitable hardware available?
Surprisingly to me, the answer seems to be yes. Here is a suggestion from a twitter conversation with @daveshah1 and others:
EasyNIC 10G would be:
The FPGA would use programmable logic to implement the PCIe endpoint, the Ethernet MAC, and the EasyNIC driver interface. The I/O interface from FPGA to PCIe would be the 4 x 5Gbps SERDES on the ECP5-5G. The I/O interface from FPGA to 10G PHY would be 32x311Mbps using ordinary I/O pins on the FPGA (which is known to support twice this bitrate for DDR3 memory.)
The cost of the FPGA seems to be ~$50 and the PHY ~$20. There are no license fees for the developer tools or hardware features thanks to full ECP5 support in the Yosys open source hardware toolchain.
The NIC might be able to have multiple 10G ports each using separate silicon and connecting to a "bifurcated" PCIe slot.
This is an exciting possibility. Overall this NIC would seem comparable to the Intel 82599. This would make it a practical NIC for many serious applications.
If we decide to move forward with this approach then we could start by developing a 1G NIC using an off-the-shelf ECP5 Versa development board that costs ~$200 and includes PCIe and 10/100/1000 RJ45 connectivity.