Open lukego opened 6 years ago
What about having a ringbuffer of <pointer, length> in MMIO space plus another register that serves as doorbell. The ringbuffer can map directly to DRAM on the device side. The doorbell register can be the tail pointer for the ringbuffer. This can also map to DRAM and the device only additionally needs to log when a write to this address was seen. But there is no need of queueing anything on the device side. When the device consumes buffers, it can write back the ring head pointer via DMA to host memory.
Suggestion from @blitz via Twitter: Avoid non-idempotent streaming writes to the same register, such as the way the host writes multiple addresses back-to-back into
TX_BLOCK_SEND
and requires the device to process all of them in FIFO order. Awkward to handle this on the hardware side? What is a better approach?