search

lulinchen / jpeg_open

A hardware MJPEG encoder and RTP transmitter
MIT License
37 stars 18 forks source link

Interesting project #4

Open greg2891 opened 1 year ago

greg2891 commented 1 year ago

hello I would like to try your project on different board - please let me know if its possible ?

lulinchen commented 1 year ago

Yes. The core code independent of FPGA structure.

greg2891 commented 1 month ago

Hello Sorry for late response. I have came back to your project and still would like to run it on ultrscale device. Unfortunately Vivado version I am using is 2023.1.1 and it is hard to get your project run. Also please can you help with missing IPs ? read_ip ../../../../work/ise/ultrascale/xiinx_GEther_PHY_AN/xiinx_GEther.xci read_ip ../../../../work/ise/ultrascale16.4/Xilinx_SGMII.xcix they were placed on your harddrive I belive ?

To be honest I would really like to test it in following scenario : -Jpeg enconder +RTP stream only so ideally it would take video in from my own video pipe and stream ove ethernet (here I would also implement my own version of Xilinx ETH(TEMAC +PCS/PCA ). Is there any chance you could rebuild this on newer Vivado version or help me /guide me how can I use it with my own video pipe and own ethernet IPs? So generally if your design could take Video in and convert to RTP and this output I would use with Xilinx TEMAC IP to stream to PC

Thanks - if I get to to some working mode I will share my results here.