uart example not working tang Nano 9K

[mhanuel26]

HI @lushaylabs ,

I am testing the uart example on the Tang Nano 9K , when I program the devices all led goes oOn but using terminal serial port does not seems to change any of them. I am selecting the only COM port that ios connected when I turn on the board, so COM pot should not be the problem, I have tested using the VSC Serial Console with same result. What others things can I try to check?

Thank you in advance for your comments,

[lushaylabs]

Hey, to first make sure it is not a synthesis issue, could you try the .fs file that is in the repo here just place this in the repo instead of your own fs file (call it the same name as your current .fs file) and then program it using the "Program Only" option from the "FPGA Toolchain" button or using openFPGALoader directly.

This .fs file has been tested so it will let us know if it is a synthesis issue which might require different compilation flags or versions, or if it is com port issue, where you might need a different driver / port in-order to interact.

Let me know if it works or not and we can take it from there

[mhanuel26]

hI @lushaylabs ,

I can confirm the original .fs file does the job. I haven't modified the code, so it is a tool synthesis issue? What would you suggest to address this?

This is the output console when build and debug

Processing uart.lushay.json
Starting FPGA Toolchain
Starting Yosys CST Checking
     /----------------------------------------------------------------------------\
     |                                                                            |
     |  yosys -- Yosys Open SYnthesis Suite                                       |
     |                                                                            |
     |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
     |                                                                            |
     |  Permission to use, copy, modify, and/or distribute this software for any  |
     |  purpose with or without fee is hereby granted, provided that the above    |
     |  copyright notice and this permission notice appear in all copies.         |
     |                                                                            |
     |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
     |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
     |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
     |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
     |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
     |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
     |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
     |                                                                            |
     \----------------------------------------------------------------------------/
    Parsing uart.v
        - Module uart parsed
    Checking if all ports are defined in constraints file
    All Ports are defined
Finished CST Checking
Starting Synthesys with Yosys (Gowin)
    Step 1:     Executing Verilog-2005 frontend: c:\Dev\tangnano9k-series-examples\uart\uart.v
    Step 2:     Executing SYNTH_GOWIN pass.
        Step 2.1:   Executing Verilog-2005 frontend: c:\OSS-CA~2\bin\../share/yosys/gowin/cells_sim.v
        Step 2.2:   Executing HIERARCHY pass (managing design hierarchy).
        Step 2.3:   Executing PROC pass (convert processes to netlists).
        Step 2.4:   Executing FLATTEN pass (flatten design).
        Step 2.5:   Executing TRIBUF pass.
        Step 2.6:   Executing DEMINOUT pass (demote inout ports to input or output).
        Step 2.7:   Executing SYNTH pass.
        Step 2.8:   Executing MEMORY_LIBMAP pass (mapping memories to cells).
        Step 2.9:   Executing TECHMAP pass (map to technology primitives).
        Step 2.10:  Executing OPT pass (performing simple optimizations).
        Step 2.11:  Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
        Step 2.12:  Executing OPT pass (performing simple optimizations).
        Step 2.13:  Executing TECHMAP pass (map to technology primitives).
        Step 2.14:  Executing OPT pass (performing simple optimizations).
        Step 2.15:  Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
        Step 2.16:  Executing OPT_CLEAN pass (remove unused cells and wires).
        Step 2.17:  Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
        Step 2.18:  Executing TECHMAP pass (map to technology primitives).
        Step 2.19:  Executing OPT_EXPR pass (perform const folding).
        Step 2.20:  Executing SIMPLEMAP pass (map simple cells to gate primitives).
        Step 2.21:  Executing ABC pass (technology mapping using ABC).
        Step 2.22:  Executing TECHMAP pass (map to technology primitives).
        Step 2.23:  Executing OPT_LUT_INS pass (discard unused LUT inputs).
        Step 2.24:  Executing SETUNDEF pass (replace undef values with defined constants).
        Step 2.25:  Executing HILOMAP pass (mapping to constant drivers).
        Step 2.26:  Executing AUTONAME pass.
        Step 2.27:  Executing HIERARCHY pass (managing design hierarchy).
        Step 2.28:  Printing statistics.
        Step 2.29:  Executing CHECK pass (checking for obvious problems).
        Step 2.30:  Executing JSON backend.

    Summary
        Number of wires:                 128
        Number of wire bits:             444
        Number of public wires:          128
        Number of public wire bits:      444
        Number of memories:                0
        Number of memory bits:             0
        Number of processes:               0
        Number of cells:                 307
            ALU                           50
            DFFE                          66
            DFFRE                         10
            DFFSE                          1
            GND                            1
            IBUF                           3
            LUT1                          29
            LUT2                           9
            LUT3                          50
            LUT4                          54
            MUX2_LUT5                     19
            MUX2_LUT6                      6
            MUX2_LUT7                      1
            OBUF                           7
            VCC                            1

Finished Synthesys
Starting PnR with NextPnR
    Series:GW1N-9C Device:GW1NR-9C Package:QFN88P Speed:C6/I5
    Packing constants..
    Packing Shadow RAM..
    Packing GSR..
    Packing IOs..
    Packing diff IOs..
    Packing IO logic..
    Packing wide LUTs..
    Packing LUT5s..
    Packing LUT6s..
    Packing LUT7s..
    Packing LUT8s..
    Packing ALUs..
    Packing LUT-FFs..
    Packing non-LUT FFs..
    Packing PLLs..
    Checksum: 0x960bcdde
    Annotating ports with timing budgets for target frequency 27.00 MHz
    Checksum: 0x960bcdde
    Placed 10 cells based on constraints.
    Creating initial analytic placement for 146 cells, random placement wirelen = 7334.
    Running main analytical placer, max placement attempts per cell = 10000.
    HeAP Placer Time: 0.31s
    Running simulated annealing placer for refinement.
    SA placement time 0.17s
    Max frequency for clock 'clk_IBUF_I_O': 100.59 MHz (PASS at 27.00 MHz)
    Max delay <async>              -> <async>             : 9.90 ns
    Max delay <async>              -> posedge clk_IBUF_I_O: 4.00 ns
    Max delay posedge clk_IBUF_I_O -> <async>             : 11.87 ns
    Checksum: 0x8ce32adf
    Find global nets...
    Routing globals...
    Routing..
    Setting up routing queue.
    Routing 770 arcs.
    Routing complete.
    Router1 time 2.89s
    Checksum: 0xa70883e7
    Max frequency for clock 'clk_IBUF_I_O': 116.85 MHz (PASS at 27.00 MHz)
    Max delay <async>              -> <async>             : 6.63 ns
    Max delay <async>              -> posedge clk_IBUF_I_O: 2.39 ns
    Max delay posedge clk_IBUF_I_O -> <async>             : 9.93 ns
    Program finished normally.

    Device Utilisation:
        VCC:               1/    1   100%
        SLICE:           222/ 8640     2%
        IOB:              10/  274     3%
        ODDR:              0/  274     0%
        MUX2_LUT5:        19/ 4320     0%
        MUX2_LUT6:         6/ 2160     0%
        MUX2_LUT7:         1/ 1080     0%
        MUX2_LUT8:         0/ 1056     0%
        GND:               1/    1   100%
        RAMW:              0/  270     0%
        GSR:               1/    1   100%
        OSC:               0/    1     0%
        rPLL:              0/    2     0%

Finished PnR
Starting Bitstream Generation with Apicula
testing. You are advised not to use it for production. 

Finished Bitstream Generation
Starting FPGA Programming with OpenFPGALoader
    write to flash
    Jtag frequency : requested 6.00MHz    found 1 devices
    index 0:
        idcode 0x100481b
        manufacturer Gowin
        family GW1N
        model  GW1N(R)-9C
        irlength 8
    File type : fs
    Parse file Parse c:\Dev\tangnano9k-series-examples\uart\uart.fs: 
    checksum 0x824a
    Done
    DONE
    bitstream header infos
    CRCCheck: ON
    Compress: OFF
    ConfDataLength: 712
    ProgramDoneBypass: OFF
    SPIAddr: 00fff000
    SecurityBit: ON
    idcode: 1100481b
    loading_rate: 0
    Jtag frequency : requested 2.50MHz    Done
    erase Flash Done
    Flash Written
    Done
    Error: Error key checkSum not found
    CRC check: Success
    displayReadReg 0001f020
        Memory Erase
        Gowin VLD
        Done Final
        Security Final
        Ready
        POR
Finished FPGA Programming
Toolchain Completed

Thank you, Manuel

[lushaylabs]

Sorry for the delay, took some time to test, it seems to be an issue due to a change done in the opensource toolchain with your version of OSS CAD Suite. I know I told you to download that version, so apologies for the confusion. I have retested all the projects using this version https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2023-02-10 and have not had any issues. Sorry again for the inconvenience and thank you for reporting the issue. The open source toolchain is currently going through a redesign and then I will update the recommended version from 2023-02-10 to the latest version once tested

[Krasnomakov]

Hello,

I am following the UART tutorial. When it comes to Tabby testing or interacting with Node via serial it is denying the access both in Tabby and when use a script. Why? How can I allow the access?

node .\serial-program.js node:internal/process/promises:289 triggerUncaughtException(err, true / fromPromise /); ^

Error: Opening COM9: Access denied Emitted 'error' event on SerialPort instance at: at SerialPort._error (C:\Users\user\Downloads\lushayLabs\tangnano9k-series-examples\uart\node_modules\@serialport\stream\dist\index.js:85:18) at C:\Users\user\Downloads\lushayLabs\tangnano9k-series-examples\uart\node_modules\@serialport\stream\dist\index.js:118:18

Node.js v20.12.2

[lushaylabs]

@Krasnomakov Im have had trouble with the UART on windows before, not sure if it is the same issue as you are having but from what I saw it is usually a driver issue.

I had to move usbser.sys from C:/Windows/system32/drivers/ (I moved it to my desktop instead) then I had to uninstall the driver in device manager for the comm port device. I then removed the device and replugged it in and instead of the previous driver it used a lib-usb driver. I uninstalled this as-well and installed the sipeed driver from here https://dl.sipeed.com/shareURL/TANG/programmer

I also downloaded the latest version of ZADIG to replace the driver for interface 0 to winusb

After that I have interface 0 using winusb and interface 1 (the serial port) using ftdibus

I am including some images of how the drivers look. Let me know if yours looks similar

[Krasnomakov]

@lushaylabs Thank you, issue resolved completely. Tested with Serial Terminal, Tabby and the script.