With the following change now creates a log of the Synthesis & Place …

[develone]

…and Route

in the files yosys-uart.log & nextpnr-uart.log

devel@pi4-50:~/tangnano9k-series-examples $ git diff diff --git a/uart/Makefile b/uart/Makefile index fa9ae97..2a28e46 100644 --- a/uart/Makefile +++ b/uart/Makefile @@ -6,11 +6,11 @@ all: uart.fs

Synthesis

uart.json: uart.v

• yosys -p "read_verilog uart.v; synth_gowin -top uart -json uart.json"

• yosys -l yosys-uart.log -p "read_verilog uart.v; synth_gowin -top uart -json uart.json"

  Place and Route

  uart_pnr.json: uart.json

• nextpnr-gowin --json uart.json --write uart_pnr.json --freq 27 --device ${DEVICE} --family ${FAMILY} --cst ${BOARD}.cst

• nextpnr-gowin -l nextpnr-uart.log --json uart.json --write uart_pnr.json --freq 27 --device ${DEVICE} --family ${FAMILY} --cst ${BOARD}.cst

  Generate Bitstream

  uart.fs: uart_pnr.json