lvgl / lvgl_esp32_drivers

Drivers for ESP32 to be used with LVGL
MIT License
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LVGL8 Not Working Maybe BUFFER Problems. ILI9341 #77

Open Trackhe opened 3 years ago

Trackhe commented 3 years ago

Device: ESP32 16mb flash Display Res: 240x320

I tried some things. Custom Buffersize. set the DISP_BUF_SIZE like:

#if defined (CONFIG_CUSTOM_DISPLAY_BUFFER_SIZE)
    #define DISP_BUF_SIZE   CONFIG_CUSTOM_DISPLAY_BUFFER_BYTES
#elif (LVGL_VERSION_MAJOR < 8)
    #if defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_ST7789)
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ST7735S
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ST7796S
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_HX8357
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_SH1107
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * LV_VER_RES_MAX)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9481
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9486
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9488
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9341
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_SSD1306
        #if defined (CONFIG_LV_THEME_MONO)
            #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * (LV_VER_RES_MAX / 8))
        #else
            #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * LV_VER_RES_MAX)
        #endif
    #elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_FT81X)
        #define DISP_BUF_LINES  40
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * DISP_BUF_LINES)
    #elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_IL3820)
        #define DISP_BUF_SIZE (LV_VER_RES_MAX * IL3820_COLUMNS)
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_RA8875
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_GC9A01)
        #define DISP_BUF_SIZE  (LV_HOR_RES_MAX * 40)
    #elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_JD79653A)
        #define DISP_BUF_SIZE ((LV_VER_RES_MAX * LV_VER_RES_MAX) / 8) // 5KB
    #elif defined (CONFIG_LV_TFT_DISPLAY_CONTROLLER_UC8151D)
        #define DISP_BUF_SIZE ((LV_VER_RES_MAX * LV_VER_RES_MAX) / 8) // 2888 bytes
    #elif defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9163C
        #define DISP_BUF_SIZE (LV_HOR_RES_MAX * 40)
    #endif
#else
    #if defined CONFIG_LV_TFT_DISPLAY_CONTROLLER_ILI9341
        #define DISP_BUF_SIZE  (240 * 10)
    #else
        #error "No display controller selected or you dont set custom buffer and use the lvgl v8+ version"
#endif
#endif

i tried also 240 * 40 On the Display change a drawed white area but i cant see the label what i set. and the task that i use dosnt fire.

LVGL programm part:

// Definition aller Objekte in dieser Klasse
lv_obj_t * gui_mainmenu_state;

// Tasks
static void gui_mainmenu_display_task_grad_update(lv_timer_t * timer);
static void gui_mainmenu_display_asyc_grad_update(void* p);

// Definition aller in dieser Datei vorkommenden Funktionen
//Events

//Styles

// Hauptmenü Ansicht

void gui_view_mainmenu(void)
{
  lv_obj_clean(lv_scr_act()); // Leere den Bildschirm
  gui_mainmenu_state = lv_label_create(lv_scr_act());
  lv_label_set_text(gui_mainmenu_state, "N.A. Grad");
  lv_obj_set_style_text_align(gui_mainmenu_state, LV_TEXT_ALIGN_CENTER, 0);
  lv_obj_align(gui_mainmenu_state, LV_ALIGN_CENTER, 0, 0);

  lv_timer_t * timer = lv_timer_create(gui_mainmenu_display_task_grad_update, 100, NULL);
}

// Tasks
static void gui_mainmenu_display_task_grad_update(lv_timer_t * timer)
{
  lv_label_set_text(gui_mainmenu_state, "0 Grad");
  lv_obj_set_style_text_align(gui_mainmenu_state, LV_TEXT_ALIGN_CENTER, 0);
  lv_obj_align(gui_mainmenu_state, LV_ALIGN_CENTER, 0, 0);   
  ESP_LOGI(TAG, "Ich Laufe\n");
}

static void gui_mainmenu_display_asyc_grad_update(void* p)
{

}

Statup Log:

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:9436
ho 0 tail 12 room 4
load:0x40078000,len:17920
load:0x40080400,len:4616
0x40080400: _init at ??:?

entry 0x40080720
I (29) boot: ESP-IDF v4.4-dev-960-gcf457d412 2nd stage bootloader
I (29) boot: compile time 13:59:25
D (29) bootloader_flash: mmu set block paddr=0x00000000 (was 0xffffffff)
I (37) boot: chip revision: 3
I (40) boot_comm: chip revision: 3, min. bootloader chip revision: 0
D (47) boot.esp32: magic e9
D (50) boot.esp32: segments 03
D (53) boot.esp32: spi_mode 02
D (56) boot.esp32: spi_speed 00
D (60) boot.esp32: spi_size 04
I (63) boot.esp32: SPI Speed      : 40MHz
I (67) boot.esp32: SPI Mode       : DIO
I (72) boot.esp32: SPI Flash Size : 16MB
D (76) boot: Enabling RTCWDT(9000 ms)
I (80) boot: Enabling RNG early entropy source...
D (86) bootloader_flash: mmu set paddr=00010000 count=1 size=c00 src_addr=10000 src_addr_aligned=10000
D (95) boot: mapped partition table 0x10000 at 0x3f400000
D (100) flash_parts: partition table verified, 5 entries
I (106) boot: Partition Table:
I (110) boot: ## Label            Usage          Type ST Offset   Length
D (117) boot: load partition table entry 0x3f400000
D (122) boot: type=1 subtype=2
I (125) boot:  0 nvs              WiFi data        01 02 00011000 00006000
D (133) boot: load partition table entry 0x3f400020
D (137) boot: type=1 subtype=1
I (141) boot:  1 phy_init         RF data          01 01 00017000 00001000
D (148) boot: load partition table entry 0x3f400040
D (153) boot: type=0 subtype=0
I (156) boot:  2 factory          factory app      00 00 00020000 000fa000
D (164) boot: load partition table entry 0x3f400060
D (169) boot: type=1 subtype=82
I (172) boot:  3 storage          Unknown data     01 82 0011a000 00edc000
I (180) boot: End of partition table
D (184) boot: Trying partition index -1 offs 0x20000 size 0xfa000
D (190) esp_image: reading image header @ 0x20000
D (195) bootloader_flash: mmu set block paddr=0x00020000 (was 0xffffffff)
D (202) esp_image: image header: 0xe9 0x06 0x02 0x04 400816dc
I (207) boot_comm: chip revision: 3, min. application chip revision: 0
V (215) esp_image: loading segment header 0 at offset 0x20018
V (220) esp_image: segment data length 0x1813c data starts 0x20020
V (227) esp_image: segment 0 map_segment 1 segment_data_offs 0x20020 load_addr 0x3f400020
I (235) esp_image: segment 0: paddr=00020020 vaddr=3f400020 size=1813ch ( 98620) map
D (243) esp_image: free data page_count 0x00000032
D (248) bootloader_flash: mmu set paddr=00020000 count=2 size=1813c src_addr=20020 src_addr_aligned=20000
V (293) esp_image: loading segment header 1 at offset 0x3815c
D (293) bootloader_flash: mmu set block paddr=0x00030000 (was 0xffffffff)
V (294) esp_image: segment data length 0x2738 data starts 0x38164
V (301) esp_image: segment 1 map_segment 0 segment_data_offs 0x38164 load_addr 0x3ffb0000
I (309) esp_image: segment 1: paddr=00038164 vaddr=3ffb0000 size=02738h ( 10040) load
D (317) esp_image: free data page_count 0x00000032
D (322) bootloader_flash: mmu set paddr=00030000 count=1 size=2738 src_addr=38164 src_addr_aligned=30000
V (336) esp_image: loading segment header 2 at offset 0x3a89c
D (338) bootloader_flash: mmu set block paddr=0x00030000 (was 0xffffffff)
V (344) esp_image: segment data length 0x5774 data starts 0x3a8a4
V (351) esp_image: segment 2 map_segment 0 segment_data_offs 0x3a8a4 load_addr 0x40080000
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

I (359) esp_image: segment 2: paddr=0003a8a4 vaddr=40080000 size=05774h ( 22388) load
D (367) esp_image: free data page_count 0x00000032
D (372) bootloader_flash: mmu set paddr=00030000 count=2 size=5774 src_addr=3a8a4 src_addr_aligned=30000
V (391) esp_image: loading segment header 3 at offset 0x40018
D (391) bootloader_flash: mmu set block paddr=0x00040000 (was 0xffffffff)
V (394) esp_image: segment data length 0x49a28 data starts 0x40020
V (401) esp_image: segment 3 map_segment 1 segment_data_offs 0x40020 load_addr 0x400d0020
0x400d0020: _stext at ??:?

I (409) esp_image: segment 3: paddr=00040020 vaddr=400d0020 size=49a28h (301608) map
D (417) esp_image: free data page_count 0x00000032
D (422) bootloader_flash: mmu set paddr=00040000 count=5 size=49a28 src_addr=40020 src_addr_aligned=40000
V (539) esp_image: loading segment header 4 at offset 0x89a48
D (539) bootloader_flash: mmu set block paddr=0x00080000 (was 0xffffffff)
V (540) esp_image: segment data length 0x135a0 data starts 0x89a50
V (546) esp_image: segment 4 map_segment 0 segment_data_offs 0x89a50 load_addr 0x40085774
0x40085774: _lock_release at /Users/trackhe/esp/esp-idf/components/newlib/locks.c:206

I (555) esp_image: segment 4: paddr=00089a50 vaddr=40085774 size=135a0h ( 79264) load
D (563) esp_image: free data page_count 0x00000032
D (568) bootloader_flash: mmu set paddr=00080000 count=2 size=135a0 src_addr=89a50 src_addr_aligned=80000
V (611) esp_image: loading segment header 5 at offset 0x9cff0
D (611) bootloader_flash: mmu set block paddr=0x00090000 (was 0xffffffff)
V (612) esp_image: segment data length 0x10 data starts 0x9cff8
V (618) esp_image: segment 5 map_segment 0 segment_data_offs 0x9cff8 load_addr 0x50000000
I (626) esp_image: segment 5: paddr=0009cff8 vaddr=50000000 size=00010h (    16) load
D (635) esp_image: free data page_count 0x00000032
D (640) bootloader_flash: mmu set paddr=00090000 count=1 size=10 src_addr=9cff8 src_addr_aligned=90000
V (649) esp_image: image start 0x00020000 end of last section 0x0009d008
D (656) bootloader_flash: mmu set block paddr=0x00090000 (was 0xffffffff)
D (663) boot: Calculated hash: af05da3e59e60c4aae9e94c18be906fc55fe166bb9207484db52462e398bc6bb
D (672) bootloader_flash: mmu set paddr=00090000 count=1 size=20 src_addr=9d010 src_addr_aligned=90000
D (681) bootloader_flash: mmu set paddr=00090000 count=1 size=20 src_addr=9d010 src_addr_aligned=90000
I (705) boot: Loaded app from partition at offset 0x20000
I (705) boot: Disabling RNG early entropy source...
D (705) boot: Mapping segment 0 as DROM
D (709) boot: Mapping segment 3 as IROM
D (713) boot: calling set_cache_and_start_app
D (717) boot: configure drom and irom and start
V (722) boot: d mmu set paddr=00020000 vaddr=3f400000 size=98620 n=2
V (728) boot: rc=0
V (730) boot: rc=0
V (733) boot: i mmu set paddr=00040000 vaddr=400d0000 size=301608 n=5
V (739) boot: rc=0
V (741) boot: rc=0
D (743) boot: start: 0x400816dc
0x400816dc: call_start_cpu0 at /Users/trackhe/esp/esp-idf/components/esp_system/port/cpu_start.c:268

D (758) efuse: In EFUSE_BLK0__DATA3_REG is used 3 bits starting with 9 bit
D (758) efuse: In EFUSE_BLK0__DATA3_REG is used 1 bits starting with 2 bit
I (763) psram: This chip is ESP32-D0WD
I (769) spiram: Found 64MBit SPI RAM device
I (772) spiram: SPI RAM mode: flash 40m sram 40m
I (777) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (784) cpu_start: Pro cpu up.
D (788) efuse: In EFUSE_BLK0__DATA3_REG is used 1 bits starting with 15 bit
D (795) efuse: In EFUSE_BLK0__DATA5_REG is used 1 bits starting with 20 bit
D (802) efuse: In EFUSE_BLK0__DATA3_REG is used 3 bits starting with 9 bit
D (809) efuse: In EFUSE_BLK0__DATA3_REG is used 1 bits starting with 2 bit
I (816) cpu_start: Starting app cpu, entry point is 0x4008162c
0x4008162c: call_start_cpu1 at /Users/trackhe/esp/esp-idf/components/esp_system/port/cpu_start.c:153

I (0) cpu_start: App cpu up.
I (1707) spiram: SPI SRAM memory test OK
D (1715) clk: RTC_SLOW_CLK calibration value: 2995930
I (1720) cpu_start: Pro cpu start user code
I (1720) cpu_start: cpu freq: 240000000
I (1720) cpu_start: Application information:
I (1725) cpu_start: Project name:     main
I (1730) cpu_start: App version:      2ccbcbe-dirty
I (1735) cpu_start: Compile time:     Jun 24 2021 21:52:04
I (1741) cpu_start: ELF file SHA256:  13b4aa0a088c247c...
I (1748) cpu_start: ESP-IDF:          v4.4-dev-960-gcf457d412
V (1754) memory_layout: reserved range is 0x3f41811c - 0x3f41815c
D (1760) memory_layout: Checking 8 reserved memory ranges:
D (1766) memory_layout: Reserved memory range 0x3f800000 - 0x3fc00000
D (1772) memory_layout: Reserved memory range 0x3ffae000 - 0x3ffae6e0
D (1779) memory_layout: Reserved memory range 0x3ffb0000 - 0x3ffb3730
D (1785) memory_layout: Reserved memory range 0x3ffe0000 - 0x3ffe0440
D (1792) memory_layout: Reserved memory range 0x3ffe3f20 - 0x3ffe4350
D (1798) memory_layout: Reserved memory range 0x40070000 - 0x40078000
D (1805) memory_layout: Reserved memory range 0x40078000 - 0x40080000
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

D (1811) memory_layout: Reserved memory range 0x40080000 - 0x40098d14
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

D (1818) memory_layout: Building list of available memory regions:
V (1824) memory_layout: Examining memory region 0x3f800000 - 0x3fc00000
V (1831) memory_layout: Region 0x3f800000 - 0x3fc00000 inside of reserved 0x3f800000 - 0x3fc00000
V (1840) memory_layout: Examining memory region 0x3ffae000 - 0x3ffb0000
V (1846) memory_layout: Start of region 0x3ffae000 - 0x3ffb0000 overlaps reserved 0x3ffae000 - 0x3ffae6e0
D (1856) memory_layout: Available memory region 0x3ffae6e0 - 0x3ffb0000
V (1863) memory_layout: Examining memory region 0x3ffb0000 - 0x3ffb8000
V (1869) memory_layout: Start of region 0x3ffb0000 - 0x3ffb8000 overlaps reserved 0x3ffb0000 - 0x3ffb3730
D (1879) memory_layout: Available memory region 0x3ffb3730 - 0x3ffb8000
V (1886) memory_layout: Examining memory region 0x3ffb8000 - 0x3ffc0000
D (1892) memory_layout: Available memory region 0x3ffb8000 - 0x3ffc0000
V (1899) memory_layout: Examining memory region 0x3ffc0000 - 0x3ffc2000
D (1906) memory_layout: Available memory region 0x3ffc0000 - 0x3ffc2000
V (1912) memory_layout: Examining memory region 0x3ffc2000 - 0x3ffc4000
D (1919) memory_layout: Available memory region 0x3ffc2000 - 0x3ffc4000
V (1926) memory_layout: Examining memory region 0x3ffc4000 - 0x3ffc6000
D (1932) memory_layout: Available memory region 0x3ffc4000 - 0x3ffc6000
V (1939) memory_layout: Examining memory region 0x3ffc6000 - 0x3ffc8000
D (1946) memory_layout: Available memory region 0x3ffc6000 - 0x3ffc8000
V (1952) memory_layout: Examining memory region 0x3ffc8000 - 0x3ffca000
D (1959) memory_layout: Available memory region 0x3ffc8000 - 0x3ffca000
V (1966) memory_layout: Examining memory region 0x3ffca000 - 0x3ffcc000
D (1973) memory_layout: Available memory region 0x3ffca000 - 0x3ffcc000
V (1979) memory_layout: Examining memory region 0x3ffcc000 - 0x3ffce000
D (1986) memory_layout: Available memory region 0x3ffcc000 - 0x3ffce000
V (1993) memory_layout: Examining memory region 0x3ffce000 - 0x3ffd0000
D (1999) memory_layout: Available memory region 0x3ffce000 - 0x3ffd0000
V (2006) memory_layout: Examining memory region 0x3ffd0000 - 0x3ffd2000
D (2013) memory_layout: Available memory region 0x3ffd0000 - 0x3ffd2000
V (2019) memory_layout: Examining memory region 0x3ffd2000 - 0x3ffd4000
D (2026) memory_layout: Available memory region 0x3ffd2000 - 0x3ffd4000
V (2033) memory_layout: Examining memory region 0x3ffd4000 - 0x3ffd6000
D (2039) memory_layout: Available memory region 0x3ffd4000 - 0x3ffd6000
V (2046) memory_layout: Examining memory region 0x3ffd6000 - 0x3ffd8000
D (2053) memory_layout: Available memory region 0x3ffd6000 - 0x3ffd8000
V (2059) memory_layout: Examining memory region 0x3ffd8000 - 0x3ffda000
D (2066) memory_layout: Available memory region 0x3ffd8000 - 0x3ffda000
V (2073) memory_layout: Examining memory region 0x3ffda000 - 0x3ffdc000
D (2079) memory_layout: Available memory region 0x3ffda000 - 0x3ffdc000
V (2086) memory_layout: Examining memory region 0x3ffdc000 - 0x3ffde000
D (2093) memory_layout: Available memory region 0x3ffdc000 - 0x3ffde000
V (2100) memory_layout: Examining memory region 0x3ffde000 - 0x3ffe0000
D (2106) memory_layout: Available memory region 0x3ffde000 - 0x3ffe0000
V (2113) memory_layout: Examining memory region 0x3ffe0000 - 0x3ffe4000
V (2120) memory_layout: Start of region 0x3ffe0000 - 0x3ffe4000 overlaps reserved 0x3ffe0000 - 0x3ffe0440
V (2129) memory_layout: End of region 0x3ffe0440 - 0x3ffe4000 overlaps reserved 0x3ffe3f20 - 0x3ffe4350
D (2139) memory_layout: Available memory region 0x3ffe0440 - 0x3ffe3f20
V (2145) memory_layout: Examining memory region 0x3ffe4000 - 0x3ffe8000
V (2152) memory_layout: Start of region 0x3ffe4000 - 0x3ffe8000 overlaps reserved 0x3ffe3f20 - 0x3ffe4350
D (2162) memory_layout: Available memory region 0x3ffe4350 - 0x3ffe8000
V (2168) memory_layout: Examining memory region 0x3ffe8000 - 0x3fff0000
D (2175) memory_layout: Available memory region 0x3ffe8000 - 0x3fff0000
V (2182) memory_layout: Examining memory region 0x3fff0000 - 0x3fff8000
D (2188) memory_layout: Available memory region 0x3fff0000 - 0x3fff8000
V (2195) memory_layout: Examining memory region 0x3fff8000 - 0x3fffc000
D (2202) memory_layout: Available memory region 0x3fff8000 - 0x3fffc000
V (2208) memory_layout: Examining memory region 0x3fffc000 - 0x40000000
D (2215) memory_layout: Available memory region 0x3fffc000 - 0x40000000
V (2222) memory_layout: Examining memory region 0x40070000 - 0x40078000
V (2229) memory_layout: Region 0x40070000 - 0x40078000 inside of reserved 0x40070000 - 0x40078000
V (2237) memory_layout: Examining memory region 0x40078000 - 0x40080000
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2244) memory_layout: Region 0x40078000 - 0x40080000 inside of reserved 0x40078000 - 0x40080000
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2253) memory_layout: Examining memory region 0x40080000 - 0x40082000
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

0x40082000: esp_backtrace_print_from_frame at /Users/trackhe/esp/esp-idf/components/esp_system/port/arch/xtensa/debug_helpers.c:86

V (2260) memory_layout: Region 0x40080000 - 0x40082000 inside of reserved 0x40080000 - 0x40098d14
0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

0x40082000: esp_backtrace_print_from_frame at /Users/trackhe/esp/esp-idf/components/esp_system/port/arch/xtensa/debug_helpers.c:86

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2269) memory_layout: Examining memory region 0x40082000 - 0x40084000
0x40082000: esp_backtrace_print_from_frame at /Users/trackhe/esp/esp-idf/components/esp_system/port/arch/xtensa/debug_helpers.c:86

0x40084000: psram_spi_init at /Users/trackhe/esp/esp-idf/components/esp32/spiram_psram.c:670 (discriminator 33)

V (2275) memory_layout: Region 0x40082000 - 0x40084000 inside of reserved 0x40080000 - 0x40098d14
0x40082000: esp_backtrace_print_from_frame at /Users/trackhe/esp/esp-idf/components/esp_system/port/arch/xtensa/debug_helpers.c:86

0x40084000: psram_spi_init at /Users/trackhe/esp/esp-idf/components/esp32/spiram_psram.c:670 (discriminator 33)

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2284) memory_layout: Examining memory region 0x40084000 - 0x40086000
0x40084000: psram_spi_init at /Users/trackhe/esp/esp-idf/components/esp32/spiram_psram.c:670 (discriminator 33)

0x40086000: lv_draw_map at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_img.c:635

V (2291) memory_layout: Region 0x40084000 - 0x40086000 inside of reserved 0x40080000 - 0x40098d14
0x40084000: psram_spi_init at /Users/trackhe/esp/esp-idf/components/esp32/spiram_psram.c:670 (discriminator 33)

0x40086000: lv_draw_map at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_img.c:635

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2300) memory_layout: Examining memory region 0x40086000 - 0x40088000
0x40086000: lv_draw_map at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_img.c:635

0x40088000: mask_mix at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:1218
 (inlined by) line_mask_flat at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:580

V (2307) memory_layout: Region 0x40086000 - 0x40088000 inside of reserved 0x40080000 - 0x40098d14
0x40086000: lv_draw_map at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_img.c:635

0x40088000: mask_mix at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:1218
 (inlined by) line_mask_flat at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:580

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2316) memory_layout: Examining memory region 0x40088000 - 0x4008a000
0x40088000: mask_mix at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:1218
 (inlined by) line_mask_flat at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:580

0x4008a000: draw_bg_img at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_rect.c:379

V (2322) memory_layout: Region 0x40088000 - 0x4008a000 inside of reserved 0x40080000 - 0x40098d14
0x40088000: mask_mix at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:1218
 (inlined by) line_mask_flat at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_mask.c:580

0x4008a000: draw_bg_img at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_rect.c:379

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2331) memory_layout: Examining memory region 0x4008a000 - 0x4008c000
0x4008a000: draw_bg_img at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_rect.c:379

0x4008c000: spi_flash_restore_cache at /Users/trackhe/esp/esp-idf/components/spi_flash/cache_utils.c:335

V (2338) memory_layout: Region 0x4008a000 - 0x4008c000 inside of reserved 0x40080000 - 0x40098d14
0x4008a000: draw_bg_img at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/draw/lv_draw_rect.c:379

0x4008c000: spi_flash_restore_cache at /Users/trackhe/esp/esp-idf/components/spi_flash/cache_utils.c:335

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2347) memory_layout: Examining memory region 0x4008c000 - 0x4008e000
0x4008c000: spi_flash_restore_cache at /Users/trackhe/esp/esp-idf/components/spi_flash/cache_utils.c:335

0x4008e000: lv_memset_00 at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/misc/lv_mem.c:472

V (2354) memory_layout: Region 0x4008c000 - 0x4008e000 inside of reserved 0x40080000 - 0x40098d14
0x4008c000: spi_flash_restore_cache at /Users/trackhe/esp/esp-idf/components/spi_flash/cache_utils.c:335

0x4008e000: lv_memset_00 at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/misc/lv_mem.c:472

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2362) memory_layout: Examining memory region 0x4008e000 - 0x40090000
0x4008e000: lv_memset_00 at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/misc/lv_mem.c:472

0x40090000: __tzcalc_limits at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/newlib/newlib/libc/time/tzcalc_limits.c:55

V (2369) memory_layout: Region 0x4008e000 - 0x40090000 inside of reserved 0x40080000 - 0x40098d14
0x4008e000: lv_memset_00 at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/lvgl/src/misc/lv_mem.c:472

0x40090000: __tzcalc_limits at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/newlib/newlib/libc/time/tzcalc_limits.c:55

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2378) memory_layout: Examining memory region 0x40090000 - 0x40092000
0x40090000: __tzcalc_limits at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/newlib/newlib/libc/time/tzcalc_limits.c:55

0x40092000: xQueueGenericCreateStatic at /Users/trackhe/esp/esp-idf/components/freertos/queue.c:341 (discriminator 1)

V (2385) memory_layout: Region 0x40090000 - 0x40092000 inside of reserved 0x40080000 - 0x40098d14
0x40090000: __tzcalc_limits at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/newlib/newlib/libc/time/tzcalc_limits.c:55

0x40092000: xQueueGenericCreateStatic at /Users/trackhe/esp/esp-idf/components/freertos/queue.c:341 (discriminator 1)

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2394) memory_layout: Examining memory region 0x40092000 - 0x40094000
0x40092000: xQueueGenericCreateStatic at /Users/trackhe/esp/esp-idf/components/freertos/queue.c:341 (discriminator 1)

0x40094000: xTaskGetAffinity at /Users/trackhe/esp/esp-idf/components/freertos/tasks.c:4209

V (2400) memory_layout: Region 0x40092000 - 0x40094000 inside of reserved 0x40080000 - 0x40098d14
0x40092000: xQueueGenericCreateStatic at /Users/trackhe/esp/esp-idf/components/freertos/queue.c:341 (discriminator 1)

0x40094000: xTaskGetAffinity at /Users/trackhe/esp/esp-idf/components/freertos/tasks.c:4209

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2409) memory_layout: Examining memory region 0x40094000 - 0x40096000
0x40094000: xTaskGetAffinity at /Users/trackhe/esp/esp-idf/components/freertos/tasks.c:4209

0x40096000: spi_ll_set_address at /Users/trackhe/esp/esp-idf/components/hal/esp32/include/hal/spi_ll.h:820
 (inlined by) spi_hal_setup_trans at /Users/trackhe/esp/esp-idf/components/hal/spi_hal_iram.c:131

V (2416) memory_layout: Region 0x40094000 - 0x40096000 inside of reserved 0x40080000 - 0x40098d14
0x40094000: xTaskGetAffinity at /Users/trackhe/esp/esp-idf/components/freertos/tasks.c:4209

0x40096000: spi_ll_set_address at /Users/trackhe/esp/esp-idf/components/hal/esp32/include/hal/spi_ll.h:820
 (inlined by) spi_hal_setup_trans at /Users/trackhe/esp/esp-idf/components/hal/spi_hal_iram.c:131

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2425) memory_layout: Examining memory region 0x40096000 - 0x40098000
0x40096000: spi_ll_set_address at /Users/trackhe/esp/esp-idf/components/hal/esp32/include/hal/spi_ll.h:820
 (inlined by) spi_hal_setup_trans at /Users/trackhe/esp/esp-idf/components/hal/spi_hal_iram.c:131

0x40098000: spi_flash_chip_generic_get_write_protect at /Users/trackhe/esp/esp-idf/components/spi_flash/spi_flash_chip_generic.c:302

V (2432) memory_layout: Region 0x40096000 - 0x40098000 inside of reserved 0x40080000 - 0x40098d14
0x40096000: spi_ll_set_address at /Users/trackhe/esp/esp-idf/components/hal/esp32/include/hal/spi_ll.h:820
 (inlined by) spi_hal_setup_trans at /Users/trackhe/esp/esp-idf/components/hal/spi_hal_iram.c:131

0x40098000: spi_flash_chip_generic_get_write_protect at /Users/trackhe/esp/esp-idf/components/spi_flash/spi_flash_chip_generic.c:302

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

V (2441) memory_layout: Examining memory region 0x40098000 - 0x4009a000
0x40098000: spi_flash_chip_generic_get_write_protect at /Users/trackhe/esp/esp-idf/components/spi_flash/spi_flash_chip_generic.c:302

V (2447) memory_layout: Start of region 0x40098000 - 0x4009a000 overlaps reserved 0x40080000 - 0x40098d14
0x40098000: spi_flash_chip_generic_get_write_protect at /Users/trackhe/esp/esp-idf/components/spi_flash/spi_flash_chip_generic.c:302

0x40080000: _WindowOverflow4 at /Users/trackhe/esp/esp-idf/components/freertos/port/xtensa/xtensa_vectors.S:1730

D (2457) memory_layout: Available memory region 0x40098d14 - 0x4009a000
V (2464) memory_layout: Examining memory region 0x4009a000 - 0x4009c000
D (2470) memory_layout: Available memory region 0x4009a000 - 0x4009c000
V (2477) memory_layout: Examining memory region 0x4009c000 - 0x4009e000
D (2484) memory_layout: Available memory region 0x4009c000 - 0x4009e000
V (2490) memory_layout: Examining memory region 0x4009e000 - 0x400a0000
D (2497) memory_layout: Available memory region 0x4009e000 - 0x400a0000
I (2504) heap_init: Initializing. RAM available for dynamic allocation:
D (2511) heap_init: New heap initialised at 0x3ffae6e0
I (2516) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
D (2522) heap_init: New heap initialised at 0x3ffb3730
I (2528) heap_init: At 3FFB3730 len 0002C8D0 (178 KiB): DRAM
I (2534) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (2540) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
D (2547) heap_init: New heap initialised at 0x40098d14
I (2552) heap_init: At 40098D14 len 000072EC (28 KiB): IRAM
I (2558) spiram: Adding pool of 4096K of external SPI memory to heap allocator
V (2567) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2573) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (2581) intr_alloc: Connected src 46 to int 2 (cpu 0)
D (2586) FLASH_HAL: extra_dummy: 1
V (2589) memspi: raw_chip_id: 1840C8

V (2593) memspi: chip_id: C84018

V (2597) memspi: raw_chip_id: 1840C8

V (2600) memspi: chip_id: C84018

D (2604) spi_flash: trying chip: issi
D (2608) spi_flash: trying chip: gd
I (2611) spi_flash: detected chip: gd
I (2616) spi_flash: flash io: dio
D (2620) cpu_start: calling init function: 0x40105a24
0x40105a24: _GLOBAL__sub_I__ZN9__gnu_cxx9__freeresEv at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/gcc/libstdc++-v3/libsupc++/eh_alloc.cc:348

D (2625) cpu_start: calling init function: 0x40105784
0x40105784: _GLOBAL__sub_I___cxa_get_globals_fast at /builds/idf/crosstool-NG/.build/HOST-x86_64-apple-darwin12/xtensa-esp32-elf/src/gcc/libstdc++-v3/libsupc++/eh_globals.cc:145

D (2630) cpu_start: calling init function: 0x40103974
0x40103974: s_set_default_wifi_log_level at /Users/trackhe/esp/esp-idf/components/esp_wifi/src/wifi_init.c:72

D (2635) cpu_start: calling init function: 0x40100cec
0x40100cec: esp_ipc_init at /Users/trackhe/esp/esp-idf/components/esp_ipc/ipc.c:88

D (2641) cpu_start: calling init function: 0x400dcba0
0x400dcba0: _GLOBAL__sub_I__ZN8SPIClassC2Eh at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/libraries/SPI/src/SPI.cpp:308

D (2645) cpu_start: calling init function: 0x400dc9cc
0x400dc9cc: _GLOBAL__sub_I__ZN6StringC2EPKc at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/WString.cpp:863

D (2650) cpu_start: calling init function: 0x400dc558
0x400dc558: _GLOBAL__sub_I__ZN6Stream9timedReadEv at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/Stream.cpp:336

D (2655) cpu_start: calling init function: 0x400dc478
0x400dc478: _GLOBAL__sub_I__ZN5Print5writeEPKhj at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/Print.cpp:374

D (2661) cpu_start: calling init function: 0x400dc398
0x400dc398: _GLOBAL__sub_I__ZN9IPAddressC2Ev at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/IPAddress.cpp:122

D (2666) cpu_start: calling init function: 0x400dc2f4
0x400dc2f4: _GLOBAL__sub_I_Serial at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/HardwareSerial.cpp:221

D (2671) cpu_start: calling init function: 0x400dc1fc
0x400dc1fc: _GLOBAL__sub_I__Z19interruptFunctionalPv at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../components/arduino/cores/esp32/FunctionalInterrupt.cpp:40

D (2676) cpu_start: calling init function: 0x400dbb24
0x400dbb24: _GLOBAL__sub_I__ZN7ADS12564initEhhhj at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../main/ADS1256.cpp:318

D (2681) cpu_start: calling init function: 0x400db9d0
0x400db9d0: _GLOBAL__sub_I_adstemps at /Volumes/Containerdisk2/GitHub/heizbadsteuerung/build/../main/main.cpp:211

D (2686) cpu_start: calling init function: 0x400d2718
0x400d2718: esp_reset_reason_init at /Users/trackhe/esp/esp-idf/components/esp_system/port/soc/esp32/reset_reason.c:73

D (2691) cpu_start: calling init function: 0x400d19b0
0x400d19b0: esp_ota_init_app_elf_sha256 at /Users/trackhe/esp/esp-idf/components/app_update/esp_app_desc.c:76

V (2697) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2703) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xC02
D (2711) intr_alloc: Connected src 17 to int 3 (cpu 0)
D (2716) cpu_start: Setting C++ exception workarounds.
D (2722) efuse: In EFUSE_BLK0__DATA3_REG is used 1 bits starting with 15 bit
D (2729) efuse: In EFUSE_BLK0__DATA5_REG is used 1 bits starting with 20 bit
V (2736) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2742) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0x40E
D (2750) intr_alloc: Connected src 24 to int 9 (cpu 0)
I (2756) cpu_start: Starting scheduler on PRO CPU.
D (0) efuse: In EFUSE_BLK0__DATA3_REG is used 1 bits starting with 15 bit
D (0) efuse: In EFUSE_BLK0__DATA5_REG is used 1 bits starting with 20 bit
V (10) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (10) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x40E
D (20) intr_alloc: Connected src 25 to int 2 (cpu 1)
I (30) cpu_start: Starting scheduler on APP CPU.
D (2830) heap_init: New heap initialised at 0x3ffe0440
D (2840) heap_init: New heap initialised at 0x3ffe4350
I (2840) spiram: Reserving pool of 32K of internal memory for DMA/internal allocations
D (2850) spiram: Allocating block of size 32768 bytes
V (2860) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): checking args
V (2860) intr_alloc: esp_intr_alloc_intrstatus (cpu 0): Args okay. Resulting flags 0xE
D (2860) intr_alloc: Connected src 16 to int 12 (cpu 0)
I (2880) HBS: Initializing
I (4280) lvgl_helpers: Display buffer size: 2400
I (4280) lvgl_helpers: Initializing shared SPI master
I (4280) lvgl_helpers: Configuring SPI host HSPI_HOST (1)
I (4290) lvgl_helpers: MISO pin: 12, MOSI pin: 13, SCLK pin: 14, IO2/WP pin: -1, IO3/HD pin: -1
I (4300) lvgl_helpers: Max transfer size: 4800 (bytes)
I (4310) lvgl_helpers: Initializing SPI bus...
D (4310) spi: SPI2 use iomux pins.
I (4320) disp_spi: Adding SPI device
I (4320) disp_spi: Clock speed: 80000000Hz, mode: 0, CS pin: 15
V (4320) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): checking args
V (4330) intr_alloc: esp_intr_alloc_intrstatus (cpu 1): Args okay. Resulting flags 0x80E
D (4340) intr_alloc: Connected src 30 to int 3 (cpu 1)
V (4340) bus_lock: device registered on bus 1 slot 0.
D (4350) spi_hal: eff: 80000, limit: 80000k(/0), 0 dummy, -1 delay
D (4360) spi_master: SPI2: New device added to CS0, effective clock: 80000kHz
V (4360) bus_lock: device registered on bus 1 slot 1.
D (4370) spi_hal: eff: 2000, limit: 80000k(/0), 0 dummy, -1 delay
D (4380) spi_master: SPI2: New device added to CS1, effective clock: 2000kHz
I (4580) ILI9341: Initialization.
V bus_lock: dev 0 acquired.
V (4580) spi_master: polling trans
V bus_lock: SPI dev changed from -1 to 0
V (4590) spi_master: polling trans done
V (4590) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4600) spi_master: polling trans
V (4600) spi_master: polling trans done
V (4600) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4610) spi_master: polling trans
V (4610) spi_master: polling trans done
V (4620) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4620) spi_master: polling trans
V (4630) spi_master: polling trans done
V (4630) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4640) spi_master: polling trans
V (4640) spi_master: polling trans done
V (4640) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4650) spi_master: polling trans
V (4650) spi_master: polling trans done
V (4660) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4660) spi_master: polling trans
V (4670) spi_master: polling trans done
V (4670) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4680) spi_master: polling trans
V (4680) spi_master: polling trans done
V (4680) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4690) spi_master: polling trans
V (4690) spi_master: polling trans done
V (4700) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4700) spi_master: polling trans
V (4710) spi_master: polling trans done
V (4710) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4720) spi_master: polling trans
V (4720) spi_master: polling trans done
V (4720) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4730) spi_master: polling trans
V (4730) spi_master: polling trans done
V (4740) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4740) spi_master: polling trans
V (4750) spi_master: polling trans done
V (4750) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4760) spi_master: polling trans
V (4760) spi_master: polling trans done
V (4760) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4770) spi_master: polling trans
V (4770) spi_master: polling trans done
V (4780) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4780) spi_master: polling trans
V (4790) spi_master: polling trans done
V (4790) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4800) spi_master: polling trans
V (4800) spi_master: polling trans done
V (4800) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4810) spi_master: polling trans
V (4810) spi_master: polling trans done
V (4820) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4820) spi_master: polling trans
V (4830) spi_master: polling trans done
V (4830) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4840) spi_master: polling trans
V (4840) spi_master: polling trans done
V (4840) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4850) spi_master: polling trans
V (4850) spi_master: polling trans done
V (4860) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4860) spi_master: polling trans
V (4870) spi_master: polling trans done
V (4870) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4880) spi_master: polling trans
V (4880) spi_master: polling trans done
V (4880) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4890) spi_master: polling trans
V (4900) spi_master: polling trans done
V (4900) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4900) spi_master: polling trans
V (4910) spi_master: polling trans done
V (4910) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4920) spi_master: polling trans
V (4920) spi_master: polling trans done
V (4920) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4930) spi_master: polling trans
V (4940) spi_master: polling trans done
V (4940) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4940) spi_master: polling trans
V (4950) spi_master: polling trans done
V (4950) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4960) spi_master: polling trans
V (4960) spi_master: polling trans done
V (4960) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4970) spi_master: polling trans
V (4980) spi_master: polling trans done
V (4980) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (4980) spi_master: polling trans
V (4990) spi_master: polling trans done
V (4990) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5000) spi_master: polling trans
V (5000) spi_master: polling trans done
V (5000) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5010) spi_master: polling trans
V (5020) spi_master: polling trans done
V (5020) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5020) spi_master: polling trans
V (5030) spi_master: polling trans done
V (5030) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5040) spi_master: polling trans
V (5040) spi_master: polling trans done
V (5040) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5050) spi_master: polling trans
V (5060) spi_master: polling trans done
V (5060) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5060) spi_master: polling trans
V (5070) spi_master: polling trans done
V (5070) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5080) spi_master: polling trans
V (5080) spi_master: polling trans done
V (5080) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5090) spi_master: polling trans
V (5100) spi_master: polling trans done
V (5100) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5100) spi_master: polling trans
V (5110) spi_master: polling trans done
V (5110) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5120) spi_master: polling trans
V (5120) spi_master: polling trans done
V (5120) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5130) spi_master: polling trans
V (5140) spi_master: polling trans done
V (5140) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5140) spi_master: polling trans
V (5150) spi_master: polling trans done
V (5150) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5160) spi_master: polling trans
V (5160) spi_master: polling trans done
V (5160) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5270) spi_master: polling trans
V (5270) spi_master: polling trans done
V (5270) bus_lock: dev 0 released.
I (5380) ILI9341: Display orientation: LANDSCAPE
I (5380) ILI9341: 0x36 command value: 0x28
V bus_lock: dev 0 acquired.
V (5380) spi_master: polling trans
V (5390) spi_master: polling trans done
V (5390) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5400) spi_master: polling trans
V (5400) spi_master: polling trans done
V (5410) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5410) spi_master: polling trans
V (5420) spi_master: polling trans done
V (5420) bus_lock: dev 0 released.
I (5420) XPT2046: XPT2046 Initialization
I (5430) gpio: GPIO[5]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 
V bus_lock: dev 0 acquired.
V (5480) spi_master: polling trans
V (5480) spi_master: polling trans done
V (5480) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5480) spi_master: polling trans
V (5490) spi_master: polling trans done
V (5490) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5490) spi_master: polling trans
V (5500) spi_master: polling trans done
V (5500) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5510) spi_master: polling trans
V (5510) spi_master: polling trans done
V (5510) bus_lock: dev 0 released.
V bus_lock: dev 0 acquired.
V (5520) spi_master: polling trans
V (5530) spi_master: polling trans done
V (5530) bus_lock: dev 0 released.
V (5530) bus_lock: dev 0 served from bg.

Related: https://github.com/lvgl/lvgl_esp32_drivers/issues/68

If i use (i get the extra line from https://github.com/lvgl/lv_sim_eclipse_sdl/blob/release/v8.0/main.c#L128-L141 that i mentioned in https://github.com/lvgl/lvgl/blob/master/docs/CHANGELOG.md#driver-changes)

    lv_disp_drv_t disp_drv;
    lv_disp_drv_init(&disp_drv);
    disp_drv.flush_cb = disp_driver_flush;
    disp_drv.hor_res = MY_DISP_HOR_RES;
    disp_drv.ver_res = MY_DISP_VER_RES;
    disp_drv.antialiasing = 1;

I get a square like:

define DISP_BUF_SIZE (320 * 40)

IMG_4372

define DISP_BUF_SIZE (320 * 100)

IMG_4371

if i use the init routine from https://github.com/lvgl/lv_port_esp32/tree/port_v8 like:

static void loop1code(void *pvParameter) {
    //tft_start();
    //startup_jpeg();

    (void) pvParameter;
    xGuiSemaphore = xSemaphoreCreateMutex();

    lv_init();
    lvgl_driver_init();

    //static lv_disp_draw_buf_t disp_buf;

    //static lv_color_t buf_1[320 * 10];
    //static lv_color_t buf_2[240 * 10];

    //lv_disp_draw_buf_init(&disp_buf, buf_1, buf_2, 320*10);

    lv_color_t* buf1 = (lv_color_t*) heap_caps_malloc(DISP_BUF_SIZE * sizeof(lv_color_t), MALLOC_CAP_DMA);
    assert(buf1 != NULL);

    /* Use double buffered when not working with monochrome displays */
    #ifndef CONFIG_LV_TFT_DISPLAY_MONOCHROME
        lv_color_t* buf2 = (lv_color_t*) heap_caps_malloc(DISP_BUF_SIZE * sizeof(lv_color_t), MALLOC_CAP_DMA);
        assert(buf2 != NULL);
    #else
        static lv_color_t *buf2 = NULL;
    #endif

    static lv_disp_draw_buf_t disp_buf;

    uint32_t size_in_px = DISP_BUF_SIZE;

    /* Initialize the working buffer depending on the selected display.
     * NOTE: buf2 == NULL when using monochrome displays. */
    lv_disp_draw_buf_init(&disp_buf, buf1, buf2, size_in_px);

    lv_disp_drv_t disp_drv;
    lv_disp_drv_init(&disp_drv);
    disp_drv.flush_cb = disp_driver_flush;

    #ifdef CONFIG_LV_TFT_DISPLAY_MONOCHROME
        disp_drv.rounder_cb = disp_driver_rounder;
        disp_drv.set_px_cb = disp_driver_set_px;
    #endif

        disp_drv.draw_buf = &disp_buf;
        lv_disp_drv_register(&disp_drv);

        /* Register an input device when enabled on the menuconfig */
    #if CONFIG_LV_TOUCH_CONTROLLER != TOUCH_CONTROLLER_NONE
        lv_indev_drv_t indev_drv;
        lv_indev_drv_init(&indev_drv);
        indev_drv.read_cb = touch_driver_read;
        indev_drv.type = LV_INDEV_TYPE_POINTER;
        lv_indev_drv_register(&indev_drv);
    #endif

    /* Create and start a periodic timer interrupt to call lv_tick_inc */
    const esp_timer_create_args_t periodic_timer_args = {
        .callback = &lv_tick_task,
        .name = "periodic_gui"
    };
    esp_timer_handle_t periodic_timer;
    ESP_ERROR_CHECK(esp_timer_create(&periodic_timer_args, &periodic_timer));
    ESP_ERROR_CHECK(esp_timer_start_periodic(periodic_timer, LV_TICK_PERIOD_MS * 1000));

    dp_views();

    while (1) {
          /* Delay 1 tick (assumes FreeRTOS tick is 10ms */
          vTaskDelay(pdMS_TO_TICKS(10));

          /* Try to take the semaphore, call lvgl related function on success */
          if (pdTRUE == xSemaphoreTake(xGuiSemaphore, portMAX_DELAY)) {
              lv_task_handler();
              xSemaphoreGive(xGuiSemaphore);
        }
      }

    /* A task should NEVER return */
        free(buf1);
    #ifndef CONFIG_LV_TFT_DISPLAY_MONOCHROME
        free(buf2);
    #endif
    vTaskDelete(NULL);
}

without

    disp_drv.hor_res = MY_DISP_HOR_RES;
    disp_drv.ver_res = MY_DISP_VER_RES;
    disp_drv.antialiasing = 1;

then i get

define DISP_BUF_SIZE (320 * 40)

IMG_4373

sorry if my writing is confuse ^^' I am happy to explain if anything is unclear

I hope this help us with lvgl8 :)

Best Regards.

C47D commented 3 years ago

Hi,

We're just started porting both lvgl_esp32_drivers and lv_port_esp32 to LVGL v8, I haven't been able to get my displays to test it at home, will try this weekend.

Trackhe commented 3 years ago

Hi,

We're just started porting both lvgl_esp32_drivers and lv_port_esp32 to LVGL v8, I haven't been able to get my displays to test it at home, will try this weekend.

any news? i want to help :)

C47D commented 2 years ago

Not really (from me), I'm a bit busy at work, but will try to take a look at this, I was trying to close all v7 related issues before starting to work on the v8 support.

Trackhe commented 2 years ago

Understandable

ogghst commented 2 years ago

i've found a possible fix. as per https://docs.lvgl.io/8.0/porting/display.html?highlight=lv_disp_draw_buf_t the flush callback must end with lv_disp_flush_ready(drv). here is the modified function:

`void ili9341_flush(lv_disp_drv_t drv, const lv_area_t area, lv_color_t * color_map) { uint8_t data[4];

/*Column addresses*/
ili9341_send_cmd(0x2A);
data[0] = (area->x1 >> 8) & 0xFF;
data[1] = area->x1 & 0xFF;
data[2] = (area->x2 >> 8) & 0xFF;
data[3] = area->x2 & 0xFF;
ili9341_send_data(data, 4);

/*Page addresses*/
ili9341_send_cmd(0x2B);
data[0] = (area->y1 >> 8) & 0xFF;
data[1] = area->y1 & 0xFF;
data[2] = (area->y2 >> 8) & 0xFF;
data[3] = area->y2 & 0xFF;
ili9341_send_data(data, 4);

/*Memory write*/
ili9341_send_cmd(0x2C);

uint32_t size = lv_area_get_width(area) * lv_area_get_height(area);

ili9341_send_color((void*)color_map, size * 2);

lv_disp_flush_ready(drv);

}`

here is my fix, this at least makes the whole screen renderable, then I am working to speedup DMA buffer (now is limited to <4096 bytes to avoid overflow and is damn slow!)