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lxschwalb / fpga_mel_filter_bank

System Verilog implementation of Mel Filter Bank
MIT License
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Can I set the frame length N as not the power of 2? #4

Closed FishSeeker closed 4 years ago

FishSeeker commented 4 years ago

Such as 640. And why must the OUT_WIDTH be a factor of 40?

lxschwalb commented 4 years ago

When the frame length is a power of 2, it allows for much more efficient hardware designs. I designed the hardware assuming that the frame size is a power of 2 in order to make it more efficient. For a different frame size you have to manually add a module doing zero padding.

This module calculates 40 filter banks. OUT_WIDTH only determines how they are output. If OUT_WIDTH is 40, they all go out in parallel in one clock cycle. If it is 4, it outputs 4 at a time taking 10 clock cycles to output all 40.

I'm adding the report I made for this project to the repo as a pdf now. That should make everything clear