Closed occheung closed 3 years ago
Modified VexRiscv_IMA variant with the following items:
DYNAMIC_TARGET
To generate the verilog, GenCoreDefault.scala is updated by adding addition options:
GenCoreDefault.scala
earlyBranch
singleCycleShift
Additional fix in GenCoreDefault.scala:
memoryTranslatorPortConfig
null
Finally, the generated files for VexRiscv_IMA variant (VexRiscxv_IMA.v & `VexRiscv_IMA.yaml) are updated.
VexRiscxv_IMA.v
Summary
Modified VexRiscv_IMA variant with the following items:
DYNAMIC_TARGET).To generate the verilog,
GenCoreDefault.scalais updated by adding addition options:earlyBranchsingleCycleShiftAdditional fix in
GenCoreDefault.scala:memoryTranslatorPortConfigparameter of IBus/DBus plugins is explicitly set tonullwhen not building a linux CPU.Finally, the generated files for VexRiscv_IMA variant (
VexRiscxv_IMA.v& `VexRiscv_IMA.yaml) are updated.