sbourdeauducq
commented
3 years ago The FPU is not enabled in the generated file here, correct?
Closed occheung closed 3 years ago
sbourdeauducq
commented
3 years ago The FPU is not enabled in the generated file here, correct?
occheung
commented
3 years ago Yes. I think we should make another variant that enables FPU instead in another patch.
It will probably be something like VexRiscv_IMAF I guess, subject to RV32 extension conventions.
Dolu1990
commented
3 years ago <3
@occheung The FPU require the data cache, f32 should be plug and play, while f64 would require some config changes as having a 64bits data cache.
If you want to try the f64, let's me know ^^
occheung
commented
3 years ago If you want to try the f64, let's me know ^^
@Dolu1990 Definitely! Also, is it possible to have the 64-bits cache with wishbone? I think the wishbone configuration is currently hardcoded to support 32-bits data width only in VexRiscv.
def getWishboneConfig() = WishboneConfig(
addressWidth = 30,
dataWidth = 32,
selWidth = 4,
useSTALL = false,
useLOCK = false,
useERR = true,
useRTY = false,
tgaWidth = 0,
tgcWidth = 0,
tgdWidth = 0,
useBTE = true,
useCTI = true
)@occheung I changed the bridge to allow more than 32 bits, let's me know if it create issues ^^.
So if you want to go with the 64 bits FPU, you can take a look into :
which show the impact on a regular 32 bits system to handle the 64 bits FPU via the includeFpu argument.
dBusWidth = if (includeFpu) 64 else 32,
loadStoreWidth = if (includeFpu) 64 else 32,=>
new DBusCachedPlugin(
config = new DataCacheConfig(
cpuDataWidth = 64,
memDataWidth = 64,
withWriteAggregation = true
...
),
....
),@occheung I changed the bridge to allow more than 32 bits, let's me know if it create issues ^^.
@Dolu1990 Thanks for the work! Though VexRiscv complained about a few things.
- cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + 2) @@ counter @@ U"00") | (cmd.address(31 downto 2) @@ U"00"))
+ cmdBridge.address := (isBurst ? (cmd.address(31 downto widthOf(counter) + addressShift) @@ counter @@ U(0, addressShift bits)) | (cmd.address(31 downto 2) @@ U(0, addressShift bits)))For the (cmd.address(31 downto 2) @@ U(0, addressShift bits) statement, the signal seems to be 33 bits wide. Perhaps you meant this instead?
(cmd.address(31 downto addressShift) @@ U(0, addressShift bits)Also, there are some errors emitted when I tried to generate the 64-bit I$.
new IBusCachedPlugin(
resetVector = argConfig.resetVector,
relaxedPcCalculation = false,
prediction = argConfig.prediction,
memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) else null,
config = InstructionCacheConfig(
cacheSize = argConfig.iCacheSize,
bytePerLine = 64,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 64,
memDataWidth = 64,
catchIllegalAccess = true,
catchAccessFault = true,
asyncTagMemory = false,
twoCycleRam = false,
twoCycleCache = true
)
)I just cherry picked your commit from the dev branch and put it onto master, do I need other commits from the dev branch as well?
Dolu1990
commented
3 years ago @occheung
Fixed :)
So, about the second error reported for the IBusCachedPlugin, did you set :
new IBusCachedPlugin(
....
config = InstructionCacheConfig(
..
addressWidth = 32,
cpuDataWidth = 32, //This should not be 64, only the refill need to be set to 64 bits
memDataWidth = 64,?
occheung
commented
3 years ago @occheung
Fixed :)
So, about the second error reported for the IBusCachedPlugin, did you set :
new IBusCachedPlugin( .... config = InstructionCacheConfig( .. addressWidth = 32, cpuDataWidth = 32, //This should not be 64, only the refill need to be set to 64 bits memDataWidth = 64,?
Thanks for the heads-up! VexRiscv with 64-bits I$ and D$ just ran the BIOS!
MiSoC BIOS
(c) Copyright 2007-2017 M-Labs Limited
Built Sep 17 2021 16:10:51
BIOS CRC passed (e2caea81)
Initializing SDRAM...
Read delays: 1:00-09 0:00-09 completed
Memtest OK
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Error: Invalid flash boot image length 0xffffffff
Booting from network...
Local IP : 192.168.1.50
Remote IP: 192.168.1.100
Unable to download boot.bin over TFTP
Network boot failed
No boot medium found
BIOS> mr 0x400000
Memory dump:
0x00400000 6f 00 40 0b o.@.
BIOS> mr 0x400000 128
Memory dump:
0x00400000 6f 00 40 0b 13 00 00 00 13 00 00 00 13 00 00 00 o.@.............
0x00400010 13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 ................
0x00400020 23 2e 11 fe 23 2c 51 fe 23 2a 61 fe 23 28 71 fe #...#,Q.#*a.#(q.
0x00400030 23 26 a1 fe 23 24 b1 fe 23 22 c1 fe 23 20 d1 fe #&..#$..#"..# ..
0x00400040 23 2e e1 fc 23 2c f1 fc 23 2a 01 fd 23 28 11 fd #...#,..#*..#(..
0x00400050 23 26 c1 fd 23 24 d1 fd 23 22 e1 fd 23 20 f1 fd #&..#$..#"..# ..
0x00400060 13 01 01 fc 97 00 00 00 e7 80 c0 09 83 20 c1 03 ............. ..
0x00400070 83 22 81 03 03 23 41 03 83 23 01 03 03 25 c1 02 ."...#A..#...%..
BIOS>
Summary
This PR bump VexRiscv to recent versions that implements FPU, and updated the generated verilog of the VexRiscv_IMA variant.
Changed build files
build.sbt: Updated to build the scala project correctly. (See post on gitter, worked immediately after updatingbuild.sbtonly)