Add RV32G variant - Githubissues

m-labs / VexRiscv-verilog

Using VexRiscv without installing Scala

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Closed occheung closed 3 years ago

occheung commented 3 years ago

This PR adds an RV32G variant. Options (fpu, double) are added to enable FPU features (F/D extension) from VexRiscv.

VexRiscv_G.v is generated using Makefile.