m-labs / VexRiscv-verilog

Using VexRiscv without installing Scala
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Makefile: Generate fewer PMP regions #15

Closed occheung closed 3 years ago

occheung commented 3 years ago

Summary

This patch is to reduce the number of PMP regions generated in VexRiscv cores from 16 to 4. ARTIQ only uses the first 4 PMP registers to implement stack overflow protection (ARTIQ PR).

Related fault

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------
     -2.453      -18.974                     34                44662        0.072        0.000                      0                44655        0.264        0.000                       0                 20490

Timing constraints are not met.

See failed build on hydra

Test

The ARTIQ gateware for nist_clock (kc705) and tester (kasli) was built using the VexRiscv_IMA variant. Timing constraints are satisfied.

kc705:

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.123        0.000                      0                49126        0.057        0.000                      0                49119        0.264        0.000                       0                 21536  

All user specified timing constraints are met.

kasli:

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.136        0.000                      0                42960        0.065        0.000                      0                42953        0.264        0.000                       0                 19546  

All user specified timing constraints are met.