Adds VexRiscv_IMA_wide variant, which is exactly the same as VexRiscv_IMA except the IBus/DBus are 64 bits wide.
This is to allow a SoC (e.g. the one on ARTIQ) to be built with
A kernel CPU that supports floating-point instruction (VexRiscv_G)
A comm CPU that does not need hard-float (VexRiscv_IMA_wide)
without inserting additional bus converters into the interconnect.
Updates dependencies and revert the makefile patch in #16. The PMP patch was merged into VexRiscv.
Allow module names/suffixes to be generated with variant name.
This is to avoid confusion when 2 different VexRiscv CPUs are included in the same SoC.
Generate/Update verilogs for VexRiscv_IMA(_wide) & VexRiscv_G.
Summary
Adds
VexRiscv_IMA_widevariant, which is exactly the same asVexRiscv_IMAexcept the IBus/DBus are 64 bits wide. This is to allow a SoC (e.g. the one on ARTIQ) to be built withwithout inserting additional bus converters into the interconnect.
VexRiscv_IMA(_wide)&VexRiscv_G.