Open sbourdeauducq opened 4 years ago
2 problems right there.
First, the current AD9910 driver seems to be unable to support a sysclk frequency that is lower than the RTIO frequency. This is demonstrated by this line in AD9910.
https://github.com/m-labs/artiq/blob/b4f24dd326e02835ecd34e3dea44d1f4c4285637/artiq/coredevice/ad9910.py#L174
With f_sysclk < f_rtio, sysclk_per_mu
is 0. Besides synchronization, this will impact POW calculations in some phase modes.
Second, the sync_clk frequency divider needs to be updated. sync_clk
frequency needs to be f_sysclk/16, since f_sysclk = f_rtio/2, sync_div
needs to be 4 in this case.
Build firmware and device database from this JSON:
Attempting to calibrate Urukul synchronization fails with "no IO_UPDATE-SYNC_CLK alignment edge found".
That was observed with Urukul 1.4. When using the default 125MHz RTIO clock and PLL setting (N=32) on the same hardware system then synchronization works.