kasli: add satellite WRPLL clock recovery

[MorganTL]

ARTIQ Pull Request

Description of Changes

Merge Part 1 before merging this PR. This is part 2 of the WRPLL port, focusing on adding satellite WRPLL clock recovery

Changes to the zynq#282 version:

• update libfringe for the stack push/pop fix
• use risc-v interrupt instead of the ARM's FIQ
• change the low pass filters to fixed point
  • risc-v FPU is much slower and reduce async performance significantly (around -25%)
  • fixed point fractional bits = 38 and i64 is used to do fixed point calculation
    • to avoid overflow, the largest fixed point fractional bits for i32 is 6 while i64 is 38
    • using 6 bits will introduce big quantization error, so i64 is used
• setting CLK_SEL during io_expander init
  • refactor to set initial out_target during io_expander init
  • prevent CLK_SEL set to low during the 2nd io_expander init after the clock switch reboot
• update TAG_OFFSET for kasli 2.0 to meet the setup/hold constraints of rx synchronizer

  Testing

Lock test

• both 125MHz & 100MHz WRPLL hold lock for the 1hr test duration
• no lose of lock during UART info!

Phase noise

• The phase noise of the WRPLL reach the noise floor of the spectrum analyzer, the real result maybe even lower than this

TAG_OFFSET calibration

• The average of 10 consecutive runs, 23890 is used as TAG_OFFSET

INFO(board_artiq::si549::wrpll): calibration successful, error zone: 7848 -> 9128, width: 31488 (345deg), middle of working region: 24872
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 7128 -> 8424, width: 31472 (345deg), middle of working region: 24160
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6488 -> 7840, width: 31416 (345deg), middle of working region: 23548
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6504 -> 7888, width: 31384 (344deg), middle of working region: 23580
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6240 -> 7568, width: 31440 (345deg), middle of working region: 23288
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6680 -> 7960, width: 31488 (345deg), middle of working region: 23704
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6376 -> 7688, width: 31456 (345deg), middle of working region: 23416
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 7664 -> 9024, width: 31408 (345deg), middle of working region: 24728
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 7288 -> 8632, width: 31424 (345deg), middle of working region: 24344
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6824 -> 8152, width: 31440 (345deg), middle of working region: 23872
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6792 -> 8184, width: 31376 (344deg), middle of working region: 23872
INFO(board_artiq::si549::wrpll): calibration successful, error zone: 6192 -> 7632, width: 31328 (344deg), middle of working region: 23296

Type of Changes

	Type
✓	:sparkles: New feature
✓	:hammer: Refactoring

Steps (Choose relevant, delete irrelevant before submitting)

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Code Changes

• [x] Check, test, and update the unittests in /artiq/test/ or gateware simulations in /artiq/gateware/test

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• [x] Split your contribution into logically separate changes (git rebase --interactive). Merge/squash/fixup commits that just fix or amend previous commits. Remove unintended changes & cleanup. See tutorial.

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Licensing

See copyright & licensing for more info. ARTIQ files that do not contain a license header are copyrighted by M-Labs Limited and are licensed under LGPLv3+.

[sbourdeauducq]

no lose of lock during UART info!

The UART isn't using interrupts, so why would it impact the lock?

[MorganTL]

no lose of lock during UART info!

The UART isn't using interrupts, so why would it impact the lock?

On zynq, using UART will disable the interrupt. So I also test that just in case.