m-labs / artiq

A leading-edge control system for quantum information experiments
https://m-labs.hk/artiq
GNU Lesser General Public License v3.0
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Unexpected Sequence Error in ARTIQ 8 #2456

Closed connorgoham closed 2 months ago

connorgoham commented 3 months ago

Bug Report

One-Line Summary

Sequence error in ARTIQ 8 that is not expected nor present in ARTIQ 7.

Issue Details

Steps to Reproduce

Minimal example experiment code:

` from artiq.experiment import *

class IdleKernelSequenceErrorBug(EnvExperiment): def build(self): self.setattr_device("core") self.setattr_device("led1") self.setattr_device("zotino0")

@kernel
def zotino_led_double_blink(self):
    wait_time = 50 * ms
    for _ in range(2):
        self.zotino0.set_leds(2 ** 8 - 1)
        delay(wait_time)
        self.zotino0.set_leds(0)
        delay(wait_time)

@kernel
def kasli_led1_double_blink(self):
    wait_time = 50 * ms
    for _ in range(2):
        self.led1.on()
        delay(wait_time)
        self.led1.off()
        delay(wait_time)

@kernel
def run(self):
    self.core.reset()
    while True:
        with parallel:
            self.kasli_led1_double_blink()
            self.zotino_led_double_blink()

`

Expected Behavior

Code runs without error blinking the Kasli SoC & Zotino LEDs.

Actual (undesired) Behavior

Your System (omit irrelevant parts)

$ ./local_run.sh -i -b 192.168.1.76 Open On-Chip Debugger 0.12.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'ftdi device_desc' not 'ftdi_device_desc' DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid' DEPRECATED! use 'ftdi channel' not 'ftdi_channel' DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init' Zynq CPU1. DEPRECATED! use 'ftdi layout_signal' not 'ftdi_layout_signal' Info : clock speed 1000 kHz Info : JTAG tap: zynq.tap tap/device found: 0x1372c093 (mfg: 0x049 (Xilinx), part: 0x372c, ver: 0x1) Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) Info : zynq.cpu.0: hardware has 6 breakpoints, 4 watchpoints Info : zynq.cpu.1: hardware has 6 breakpoints, 4 watchpoints Info : starting gdb server for zynq.cpu.0 on 3333 Info : Listening on port 3333 for gdb connections Info : JTAG tap: zynq.tap tap/device found: 0x1372c093 (mfg: 0x049 (Xilinx), part: 0x372c, ver: 0x1) Info : JTAG tap: zynq.dap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) Warn : zynq.cpu.0: ran after reset and before halt ... Warn : zynq.cpu.1: ran after reset and before halt ... Info : zynq.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT Info : zynq.cpu.1: MPIDR level2 0, cluster 0, core 1, multi core, no SMT target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x000001d3 pc: 0xffffff34 MMU: disabled, D-Cache: disabled, I-Cache: disabled target halted in ARM state due to debug-request, current mode: System cpsr: 0x200001df pc: 0xffffff28 MMU: disabled, D-Cache: disabled, I-Cache: disabled

$ artiq_coremgmt log [ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting... [ 0.005248s] INFO(runtime): gateware ident: brittonlab-legacy-trap [ 0.016691s] INFO(libboard_zynq::i2c): PCA9548 detected [ 0.176446s] INFO(runtime::rtio_clocking): using 100MHz reference to make 125MHz RTIO clock with PLL [ 0.549612s] INFO(libboard_artiq::si5324): waiting for Si5324 lock... [ 2.689183s] INFO(libboard_artiq::si5324): ...locked [ 2.694394s] INFO(runtime::rtio_clocking): Switching SYS clocks... [ 2.750995s] INFO(runtime::rtio_clocking): SYS CLK switched successfully [ 2.757767s] INFO(runtime::rtio_clocking): SYS PLL locked [ 2.768435s] INFO(libboard_zynq::i2c): PCA9548 detected [ 2.805309s] INFO(runtime::comms): network addresses: MAC=fc-0f-e7-07-7b-df IPv4=192.168.1.76 IPv6-LL=fe80::fe0f:e7ff:fe07:7bdf IPv6: no configured address [ 2.842086s] INFO(runtime::comms): Loading startup kernel... [ 2.847976s] INFO(runtime::comms): Starting startup kernel... [ 2.853796s] INFO(ksupport::kernel::core1): kernel starting [ 4.123215s] INFO(ksupport::kernel::core1): kernel finished [ 4.128863s] INFO(runtime::comms): Startup kernel finished! [ 6.634090s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full } [ 251.135660s] INFO(runtime::mgmt): received connection

sbourdeauducq commented 3 months ago

Try disabling event spreading. https://github.com/m-labs/artiq/issues/1881

sbourdeauducq commented 3 months ago

Also is this over DRTIO?

connorgoham commented 2 months ago

No, the core device is in standalone configuration.

connorgoham commented 2 months ago

Confirming that when changing the default value of enable_spread to False (line 15, commit d46e949f), then rebuilding the Kasli-SoC gateware using artiq-zynq with the modified ARTIQ source, the unexpected sequence errors cease.