feature request: DDS bus reset

m-labs / artiq

A leading-edge control system for quantum information experiments

https://m-labs.hk/artiq

GNU Lesser General Public License v3.0

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feature request: DDS bus reset #35

Closed ghost closed 9 years ago

ghost commented 9 years ago

Command to reset all DDSs on DDS bus without requirement to reset FPGA.

jordens commented 9 years ago

Rationale? I can only imagine needing to reset the DDSs (do you want the bus/phy logic or the DDS) if you hit a bug in ARTIQ.

ghost commented 9 years ago

Use scenario: Artiq user suspects flakey DDS/TTL bus is resulting in erroneous frequency/phase. Reset of bus can test this.

pull rest pin on DDS
reprogram configuration register
continue with whatever experiment is scheduled next

jordens commented 9 years ago

Sounds like the tools that are planned and already there are much better at confirming/excluding flakey DDS/TTL hardware and bugs in ARTIQ than a DDS reset would ever be.

sbourdeauducq commented 9 years ago

There is artiq.coredevice.dds.DDS.init(), but as Robert points out, you probably should not really need to use it.

ghost commented 9 years ago

At present the reset button on the Kintex7 eval board is accessible with the FMC connector attached. This may not be the case in the future if things get boxed up.

At present the reset button on the Pipistrello is difficult to access when the TTL/DDS bus adapter PCB is attached to its headers.

Its good to know about artiq.coredevice.dds.DDS.init(). -Joe

On Sat, Jun 20, 2015 at 6:16 PM, Robert Jordens notifications@github.com wrote:

Rationale? I can only imagine needing to reset the DDSs (do you want the bus/phy logic or the DDS) if you hit a bug in ARTIQ.

— Reply to this email directly or view it on GitHub https://github.com/m-labs/artiq/issues/35#issuecomment-113844139.

jordens commented 9 years ago

This is about DDS reset/init. FPGA reset/init is a different problem. But if somebody needs it it is always a bug and never a solution.

sbourdeauducq commented 9 years ago

I believe this can be resolved by using artiq.coredevice.dds.DDS.init() in the worst case. Please open a new issue if you have trouble resetting the FPGA.