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m-labs / artiq

A leading-edge control system for quantum information experiments
https://m-labs.hk/artiq
GNU Lesser General Public License v3.0
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input-only TTLs #581

Open jordens opened 7 years ago

jordens commented 7 years ago

At least on Xilinx, an input-only pin have much wider IOStandard compatibility (you can have an LVDS_25 input on a VCCIO=3.3 bank but not an output).

Cleanup (make this less of a hack) https://github.com/m-labs/artiq/commit/a91ed8394c2964bc335747f92a0ece5486b8009a and take: https://github.com/m-labs/artiq/commit/279f0d568dd96dc4966ebc6862cd2ec0562d742b

sbourdeauducq commented 7 years ago

Do the Xilinx tools complain when you use the regular I+O PHY?

jordens commented 7 years ago

Yes. They don't allow it.

sbourdeauducq commented 7 years ago

Is that really necessary considering that sysref sampling will use a more precise and different IDELAY scan eventually?

jordens commented 7 years ago

It's not required for sysref. But it's a feature. And if somebody wants/needs it this is how to do it. Leave it around.

jordens commented 6 years ago

differential channels were implemented 95c885b580a8d09860c39fe54d82a0a1ab915ed9