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m-labs / jesd204b

JESD204B core for Migen/MiSoC
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transceiver initialization/CGS at 10 GHz #6

Closed jordens closed 7 years ago

jordens commented 8 years ago

For me, with either Xxdlysreset high or skipping phase align, the initialization is about 50% reliable. It either fails to do CGS or SYNC is low. @enjoy-digital ist this reliable for you?

enjoy-digital commented 8 years ago

It seemed, but I'll do more tests soon at 5gbps/10gbps and have a closer look at the initialization in Xilinx example designs.

enjoy-digital commented 8 years ago

I contacted a Xilinx FAE on this point to see if we can have some support, let's wait the answer.

enjoy-digital commented 8 years ago

No answer from the FAE, going to do this:

enjoy-digital commented 8 years ago

https://github.com/m-labs/jesd204b/commit/a9e4ab11048752130406cc1c9496db47ec1edbd5 remove the workarounds and follow strictly the Xilinx recommendations. Simulation was not working before without a workaround, this is now working.

Core + AD9154 init still seems to fail sometimes, but I'm no longer sure this is related to transceiver initialization but maybe something else. When it fails here, resets are deasserted on phys (meaning transceivers were able to finish initialization sequence) and it seems AD9154 receives CGS correctly (CODEGRPSYNC = 0x0f), releases SYNC but then reasserts SYNC. Going to continue investigating...

jbqubit commented 8 years ago

Thank you for the update.

Joe Britton Sensors and Electron Devices Army Research Lab 2800 Powder Mill Rd Adelphi, MD 20783 301-394-3130 joseph.w.britton5.civ@mail.mil

On Thu, Oct 27, 2016 at 7:38 AM, enjoy-digital notifications@github.com wrote:

a9e4ab1 https://github.com/m-labs/jesd204b/commit/a9e4ab11048752130406cc1c9496db47ec1edbd5 remove the workarounds and follow strictly the Xilinx recommendations. Simulation was not working before without a workaround, this is now working.

Core + AD9154 init still seems to fail sometimes, but I'm no longer sure this is related to transceiver initialization but maybe something else. When it fails here, resets are deasserted on phys (meaning transceivers were able to finish initialization sequence) and it seems AD9154 receives CGS correctly (CODEGRPSYNC = 0x0f), releases SYNC but then reasserts SYNC. Going to continue investigating...

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sbourdeauducq commented 7 years ago

@enjoy-digital Any progress on that?

sbourdeauducq commented 7 years ago

Also, the datasheet says that the AD9154 can re-assert SYNCOUT if it loses synchronization. Losing synchronization seems to be a characteristic of some ADI chips (e.g. AD9914) - maybe this is "normal"? Does this keep doing that or does it behave if you do another CGS after SYNCOUT is reasserted?

jordens commented 7 years ago

It is somewhat configurable when and if it asserts SYNC. See the datasheet. It works if you repeat the sequence until it is happy. That's the workaround I am using. I would not extrapolate from one chip's problems with a clock divider to another chip's serial link. There is probably not much silicon in common.

enjoy-digital commented 7 years ago

Fixed via https://github.com/m-labs/jesd204b/commit/38f065e821344eda37a800c6aed03710e08fa10e.

jbqubit commented 7 years ago

Does Analog Devices agree that loosing sync is normal?? -Joe

On Fri, Nov 11, 2016 at 3:49 AM Sébastien Bourdeauducq < notifications@github.com> wrote:

Also, the datasheet says that the AD9154 can re-assert SYNCOUT if it loses synchronization. Losing synchronization seems to be a characteristic of some ADI chips (e.g. AD9914) - maybe this is "normal"? Does this keep doing that or does it behave if you do another CGS after SYNCOUT is reasserted?

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-- Joe Britton Sensors and Electron Devices Army Research Lab 2800 Powder Mill Rd Adelphi, MD 20783 301-394-3130 joseph.w.britton5.civ@mail.mil

enjoy-digital commented 7 years ago

Loosing sync is not normal, but can happen and that's a situation we should be able to recover from. Here the issue was more related to initialization: from time to time CGS pass, the DAC then set SYNC to 1 but then ILAs fails and the DAC set SYNC to 0 to request a re-initialization. Once initialization is done correctly, it seems we don't loose SYNC. (I'll monitor that with the new counter)