Migen Simulation ClockDomainsRenamer renaming error

[cr1901]

Any attempt to define a clock domain manually in a Migen source file that uses a simulation will cause simulations to fail. Migen decorates the clk and rst signals with a trailing number, either in the top level simulation module or the DUT module, but does not decorate the clk and rst signals in the other module with the same trailing number. This causes undefined references in simulators such as iverilog.

Migen should recognize in the context of simulations that the clk and rst signals in both the DUT and top level modules are in fact the same signal defined twice.

This bug is demonstrated in the following gist: https://gist.github.com/cr1901/8fb5298fe9982456b9d4

A workaround for the time being is to conditionally define clock domains to be defined depending on whether the user wants to simulate the module, or use the module as part of synthesis (e.g. if __name__ == "__main__").

[sbourdeauducq]

Not an issue in the new simulator.