search

m-labs / migen

A Python toolbox for building complex digital hardware
https://m-labs.hk/migen
Other
1.23k stars 210 forks source link

Fix Signal initialization when max=1 #295

Closed andelf closed 3 weeks ago

andelf commented 3 weeks ago

It's used in migen's Memory type:

https://github.com/m-labs/migen/blob/c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8/migen/fhdl/specials.py#L291-L298

This bug causes Memory initialization to fail when depth=1.

I found this(assert fail) when using WS2812 with nleds=1 in LiteX.

sbourdeauducq commented 3 weeks ago

This is not correct. min=0 (default) with max=1 means the signal value is always in the interval [0;1[, i.e. it is a constant zero. This change creates a 1-bit signal that can take values 0 and 1.

andelf commented 3 weeks ago

Thanks for your clarification. I try to fix the wrong usage in LiteX.

andelf commented 3 weeks ago

BTW. Is Memory(32, 1)(memory with depth=1) illegal?

sbourdeauducq commented 3 weeks ago

No, but it should be a register. Either way you'd need to implement some corner cases: (1) zero width signal and whether the memory is still correct with such an address signal, or (2) depth=1 memory turned into a register