Closed jordens closed 7 years ago
from migen import *
class TB(Module):
def __init__(self, n):
self.n = n
self.r = Signal(n, reset=0b10)
self.comb += self.r[0].eq(self.r[-1])
self.sync += self.r[1:].eq(self.r)
self.out = []
def run(self):
for i in range(2*self.n):
self.out.append((yield self.r))
yield
n = 3
tb = TB(n)
run_simulation(tb, tb.run(), vcd_name="t.vcd")
assert tb.out == [2, 4, 1, 2, 4, 1], tb.out
# AssertionError: [2, 2, 2, 2, 2, 2]
Looks like this is due to bit-mixing of combinatorial/synchronous assignments.
original issue is fixed
A circular shift register:
As it is written, it does not do much. But when either of the two changes are done,
sr
is not handled in the simulation and does not appear in the vcd.