I have a design with matrix of DSPs that is supposed to re-use the DSP cell. I name each with instantiation of the DSP cell using setattr to make them easy to track down during VCD traces like so:
arr = []
for r in range(Params["rows"]):
temp = []
for c in range(Params["cols"]):
#add cell as named submodule
cell = Cell(WIDTH=Params["WIDTH"])
setattr(m.submodules,f"cell_r{r}_c{c}",cell)
#externally expose sums
m.d.comb += self.sums[r][c].eq(cell.SUM)
temp.append(cell)
arr.append(temp)
When I have nmigen convert to verilog however, an identical verilog module is created for each cell as shown below:
Is it possible to have the emitted verilog re-use one DSP cell?
I guess one question one could always ask is how could nMigen know one instantiation of a DSP cell is identical to the next.
I have a design with matrix of DSPs that is supposed to re-use the DSP cell. I name each with instantiation of the DSP cell using
setattr
to make them easy to track down during VCD traces like so:When I have nmigen convert to verilog however, an identical verilog module is created for each cell as shown below:
Is it possible to have the emitted verilog re-use one DSP cell? I guess one question one could always ask is how could nMigen know one instantiation of a DSP cell is identical to the next.