m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
https://nmigen.org
Other
646 stars 55 forks source link

Update UART Example so that acknowledging RX data sets RX ready low. #344

Open newhouseb opened 3 years ago

newhouseb commented 3 years ago

The UART example code currently sets rx_rdy high when data has been received. I had assumed that setting rx_ack to high would clear this until data is ready again, but in the existing implementation rx_rdy only goes low when new data arrives. This small diff changes rx_ack to clear rx_rdy so that a user can acknowledge data after the first byte and then wait on rx_rdy for the next one. It also updates the simulation to verify that the right thing happens.

I suppose this could've been design with the intent that the user strobes out a signal when rx_rdy goes from low to high, but I'm not sure what the use of rx_ack is if this was the intended design. Sorry if I'm being oblivious, but if I am, feel free to close out this diff.