mabrains / caravel_user_project_ldo

Completed LDO Design for Skywaters 130nm
GNU Lesser General Public License v2.1
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Stability testbench seems problematic #4

Open ChrisZonghaoLi opened 1 year ago

ChrisZonghaoLi commented 1 year ago

Greetings,

I just wanted to point out that the stability script you provided here is actually problematic, see below: *Stability_Analysis .control alter IL 0 alter Vs AC =0 alter Vt AC=1 ac dec 10 1 1G plot vdb(out) plot (180/pi)*vp(out) let ph= (180/pi)*vp(out) meas ac pm FIND ph WHEN vdb(out)=0 .endc

which I copied from here: https://github.com/mabrains/caravel_user_project_ldo/blob/main/xschem/ldo_v2.spice

With the approach you took, this only finds the open-circuit voltage loop gain, and you are missing short-circuit current loop gain.

Please read this: https://www.eecg.toronto.edu/~johns/ece331/lecture_notes/22_LG_simulation.pdf

Therefore, I am not sure how did you obtain the phase margin from the loop-stability analysis, as I think your approach is wrong.

atorkmabrains commented 1 year ago

@ChrisZonghaoLi Please check: https://github.com/mabrains/Analog_blocks/blob/main/scripts/ldo_corners_v4.py

atorkmabrains commented 1 year ago

@ChrisZonghaoLi I'll get back to you about Open vs Closed loop simulation.

atorkmabrains commented 1 year ago

@ChrisZonghaoLi and @Ahmedredamohamed2022 Please ignore whatever here in that repo from the simulation point of view. GDS is only correct here in that repo.

The correct simulation is here: https://github.com/mabrains/Analog_blocks/blob/main/scripts/ldo_corners_v4.py#LL112C5-L112C8

We used the high L and high C method for loop simulation. Please check the link above.

We used resistive load to be able to simulate a specific load current. We have simulated at different capacitive loads as well. But not included in the above script.

But again, remember the models for skywaters here are totally unusable.

ChrisZonghaoLi commented 1 year ago

I think "totally unusable" may be an overstatement, and I have seen some people mention they have taped out their (analog) chip but observe the discrepancy between the simulation and measurement results. You are just not going to get the chip work exactly as you expect from the simulations especially if your W is very large since the bin size is larger than when W is small.

atorkmabrains commented 1 year ago

@ChrisZonghaoLi well, we approached this in a different way. Hopefully, the idea might stand some ground. I forced my team to use only the sizes available in the simulation models "Bins" to try to get it to work. And if they need larger size, they can use "m"/"nf". You might find some sizes in our design that doesn't fit this rule. But that's how we tried to approach this.

I really appreciate taking interest in my team's design. Keep in mind that those designs are done by recent grades and might have some issues and we do it at our spare time as we are not paid for that effort.

I was wondering if we could setup a meeting to get to know you.

atorkmabrains commented 1 year ago

@ChrisZonghaoLi Forgot to thank you for the notes that you have shared here.

ChrisZonghaoLi commented 1 year ago

@ChrisZonghaoLi well, we approached this in a different way. Hopefully, the idea might stand some ground. I forced my team to use only the sizes available in the simulation models "Bins" to try to get it to work. And if they need larger size, they can use "m"/"nf". You might find some sizes in our design that doesn't fit this rule. But that's how we tried to approach this.

I really appreciate taking interest in my team's design. Keep in mind that those designs are done by recent grades and might have some issues and we do it at our spare time as we are not paid for that effort.

I was wondering if we could setup a meeting to get to know you.

Your idea makes sense and this might be the best practice by far. Sure we can have a chat if you would like to, for more information you can reach me personally through my email: zonghao.lee@gmail.com. Thanks!