Use MAGICA tool to generate 250nm circuit layout

[Sixlvd]

Hello！Magical is a good job ！ Now we want to use MAGICAL to realize the circuit designed by CSMS 250nm process, but when we change modify mock.techfile and techfile.simple in mockfile，it will report index error just as below. May I ask whether MAGICAL supports modification for 250nm or how can we modify according to your two file examples, please give some suggestions，thank you very much! BEST WISHES!

mkdir: cannot create directory 'gds': File exists

MAGICAL: Machine Generated Analog IC Layout            
    https://github.com/magical-eda/MAGICAL

======================================================== [I] parameters = {'spectre_netlist': 'AMP.sp', 'hspice_netlist': None, 'simple_tech_file': '../28nmPDK/techfile.simple', 'resultDir': './'} Traceback (most recent call last): File "../../flow/python/Magical.py", line 43, in db.parse() #parsing the input files File "/MAGICAL/MAGICAL/flow/python/MagicalDB.py", line 20, in parse self.parse_simple_techfile(self.params.simple_tech_file) File "/MAGICAL/MAGICAL/flow/python/MagicalDB.py", line 31, in parse_simple_techfile magicalFlow.parseSimpleTechFile( params, self.techDB) IndexError: vector::_M_range_check: __n (which is 4294967295) >= this->size() (which is 500)

[krzhu]

Hello, For the error you mentioned, just make a directory called "gds" in the work area you run the tool. But transferring to a new technology might need changes on the device generator to pass LVS. You can edit our device generator on your side. We are not familar with your process so I am not knowledgable about its details.

You can contact Prof. David Z. Pan if interested in a more deep dive and collabrating with us.

Thanks, Keren

On Sun, Dec 12, 2021 at 23:18 Sixlvd @.***> wrote:

Hello！Magical is a good job ！ Now we want to use MAGICAL to realize the circuit designed by CSMS 250nm process, but when we change modify mock.techfile and techfile.simple in mockfile，it will report index error just as below. May I ask whether MAGICAL supports modification for 250nm or how can we modify according to your two file examples, please give some suggestions，thank you very much! BEST WISHES! mkdir: cannot create directory 'gds': File exists

MAGICAL: Machine Generated Analog IC Layout

https://github.com/magical-eda/MAGICAL

======================================================== [I] parameters = {'spectre_netlist': 'AMP.sp', 'hspice_netlist': None, 'simple_tech_file': '../28nmPDK/techfile.simple', 'resultDir': './'} Traceback (most recent call last): File "../../flow/python/Magical.py", line 43, in db.parse() #parsing the input files File "/MAGICAL/MAGICAL/flow/python/MagicalDB.py", line 20, in parse self.parse_simple_techfile(self.params.simple_tech_file) File "/MAGICAL/MAGICAL/flow/python/MagicalDB.py", line 31, in parse_simple_techfile magicalFlow.parseSimpleTechFile( params, self.techDB) IndexError: vector::_M_range_check: __n (which is 4294967295) >= this->size() (which is 500)

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[Sixlvd]

Thanks, I see your mock. techfile and techfile. simple in mockfile that have deleted other techlayers and numbers of the process（40nm，your example files show as below）. Is the deletion regular? Because there are hundreds of techlayers and numbers under one process. Our current 250nm has all techLayers in mock. techfile and techfile. simple file without deleting them. Is there an indexing error in the following report because some techlayers were not removed in mock. techfile and techfile. simple file?

magicalFlow.parseSimpleTechFile( params, self.techDB) IndexError: vector::_M_range_check: __n (which is 4294967295) >= this->size() (which is 500)

mock.techfile： techLayers( ;( techLayer number abbreviation ) ;( --------- ------ ------------ ) ( OD 6 OD ) ( PO 17 PO ) ( CO 30 CO ) ( M1 31 M1 ) ( M2 32 M2 ) ( M3 33 M3 ) ( M4 34 M4 ) ( M5 35 M5 ) ( M6 36 M6 ) ( M7 37 M7 ) ( VIA1 51 VIA1 ) ( VIA2 52 VIA2 ) ( VIA3 53 VIA3 ) ( VIA4 54 VIA4 ) ( VIA5 55 VIA5 ) ( VIA6 56 VIA6 ) )

techfile. Simple： NW 3 OD 6 VTL_N 12 VTL_P 13 PO 17 OD_25 18 PP 25 NP 26 RPO 29 CO 30 M1 31 M2 32 M3 33 M4 34 M5 35 M6 36 M7 37 M8 38 M9 39 M10 40 VIA1 51 VIA2 52 VIA3 53 VIA4 54 VIA5 55 VIA6 56 VIA7 57 VIA8 58 VIA9 59 TECHDB 63 VTH_N 67 VTH_P 68 RPDMY 115 RH 117 MRDMY 150 TSV_PPI 155 STDPIN 171 LVS_DUMMY 208

[krzhu]

This is not an "index" error. The problem is more likely due to some typo in input files. That function is for reading the techfile. Simple file, which is just a simple files containing the layer index in GDS and its layer name.

The parsing function is at https://github.com/magical-eda/MAGICAL/blob/199ab0719f85f74c79bf85a556118b132988a5fe/flow/cpp/magical_flow/src/parser/ParseSimpleTech.cpp#L5 It just reads every line in the file and assume there are two words in each line. I guess one possibility is that you have an empty line in the input file which makes it read an empty number (become 4294967295 in Uint-32). I admit the parsing function here is poorly written.

After reading in, it just record the number and names in several arrays and maps. https://github.com/magical-eda/MAGICAL/blob/199ab0719f85f74c79bf85a556118b132988a5fe/flow/cpp/magical_flow/src/db/TechDB.h#L85

BTW, we do assume all GDS layer ID is below 500. If you want to change it, you can do it by editing this line: https://github.com/magical-eda/MAGICAL/blob/199ab0719f85f74c79bf85a556118b132988a5fe/flow/cpp/magical_flow/src/global/constant.h#L15

Thanks, Keren

On Mon, Dec 13, 2021 at 12:26 AM Sixlvd @.***> wrote:

Thanks, I see your mock. techfile and techfile. simple in mockfile that have deleted other techlayers and numbers of the process（40nm，your example files show as below）. Is the deletion regular? Because there are hundreds of techlayers and numbers under one process. Our current 250nm has all techLayers in mock. techfile and techfile. simple file without deleting them. Is there an indexing error in the following report because some techlayers were not removed in mock. techfile and techfile. simple file?

magicalFlow.parseSimpleTechFile( params, self.techDB) IndexError: vector::_M_range_check: __n (which is 4294967295) >= this->size() (which is 500)

mock.techfile： techLayers( ;( techLayer number abbreviation ) ;( --------- ------ ------------ ) ( OD 6 OD ) ( PO 17 PO ) ( CO 30 CO ) ( M1 31 M1 ) ( M2 32 M2 ) ( M3 33 M3 ) ( M4 34 M4 ) ( M5 35 M5 ) ( M6 36 M6 ) ( M7 37 M7 ) ( VIA1 51 VIA1 ) ( VIA2 52 VIA2 ) ( VIA3 53 VIA3 ) ( VIA4 54 VIA4 ) ( VIA5 55 VIA5 ) ( VIA6 56 VIA6 ) )

techfile. Simple： NW 3 OD 6 VTL_N 12 VTL_P 13 PO 17 OD_25 18 PP 25 NP 26 RPO 29 CO 30 M1 31 M2 32 M3 33 M4 34 M5 35 M6 36 M7 37 M8 38 M9 39 M10 40 VIA1 51 VIA2 52 VIA3 53 VIA4 54 VIA5 55 VIA6 56 VIA7 57 VIA8 58 VIA9 59 TECHDB 63 VTH_N 67 VTH_P 68 RPDMY 115 RH 117 MRDMY 150 TSV_PPI 155 STDPIN 171 LVS_DUMMY 208

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[Sixlvd]

You're too modest！Magic is good enough！ Looking forward to learning more about MAGICAL!

Thanks a lot for your help! Have a nice day ! Sixlvd

[Sixlvd]

Hello, I also want to ask you several questions about MAGICAL！ Q1: I have modified your example and run my own 250nm circuit. I find the following error when the metal layer is less than six layers (both run your examples and our circuits): ` DrGridRoute::runNRR Iteration 0 Unrouted nets 2, VDD GND

DrGridAstar::run Route net GND, Sym: 0, SelfSym: 0, StrictDRC: 1

python3: /tmp/pip-req-build-rsalgwvt/src/dr/drGridAstar.cpp:1046: bool ANAROUTE::DrGridAstar::bInsideGuide(const ANAROUTE::DrGridAstarNode*): Assertion `u.z() < (Int_t)_cir.vSpatialNetGuides(_net.idx()).size() and u.z() > 0' failed.

Aborted (core dumped) ` So, does the MAGICAL algorithm set a minimum of 6 metal layers for generating a layout and the sixth layer is set to be power layer ？Because I find your example: a simple operational amplifier which uses at least 6 metal layers to draw layout and the top(6) layer is power layer .

I also find TestSimpleTechParser.cpp and layer.simple.tech in /MAGICAL/flow/cpp/magical_flow/unittest , it only defines to Metal 5, are these related to the number of metal layers defined by mgaical algorithm?

Q2: Another problem is whether MAGICAL algorithm has set some small range values for spacing and width, because I found the values of spacing and width in the lef file of the 250nm process are much larger than those in 40nm, which maybe cause MAGICAL to report errors and fail to draw layout.(I run 28nm in MAGICAL is ok, while 250nm is failed)

Looking forward to your busy schedule to take time to solve my problems！Thanks , Sixlvd

[krzhu]

You can try disabling the special power routing strategy by setting all nets to be signal (https://github.com/magical-eda/MAGICAL/blob/199ab0719f85f74c79bf85a556118b132988a5fe/flow/python/PnR.py#L294)

[Sixlvd]

Thanks, can this magic be directly extended to 250nm? I find that your team writes hard codes in MAGICAL and the code seems to directly fix the content of metal layer and other layer names.

[krzhu]

Sorry for the delay. It's difficult to directly extend to 250 nm. I guess the bottleneck is on device and design rules. It's always hard to directly port a EDA tool to a new technology.

We actually have a in developing towards the opensource Skywater 130nm PDK. Due the limit of the Skywater PDK, it cannot completely support the whole MAGICAL function in 40nm, but we have already got some working examples. Maybe you can take it for an example and investigate its difference from the main branch. https://github.com/magical-eda/MAGICAL/tree/skywater

[706697916]

@krzhu I find that the page of skywater is removed. Can we have an easy way to change the PDK of MAGICAL?