Parameter file is not working

[AmrMohamedRashed]

I am trying to change any parameters for M1 for example from " MAGICAL/examples/mockPDK/mock.lef " but the generated layout is the same and Layout of M1 is not changed. Kindly how can one change width, spacing, enclosure ... etc or any other parameter ?

[krzhu]

It's always hard to directly port a EDA tool to a new technology.

We actually have a in developing towards the opensource Skywater 130nm PDK. Due the limit of the Skywater PDK, it cannot completely support the whole MAGICAL function in 40nm, but we have already got some working examples. Maybe you can take it for an example and investigate its difference from the main branch. https://github.com/magical-eda/MAGICAL/tree/skywater

[AmrMohamedRashed]

@krzhu I do not mean porting EDA tool to a new technology. I am using the mock PDK provided with MAGICAL tool. changing parameters of "MAGICAL/examples/mockPDK/mock.lef" does not change the generated gds. How can I change the width of M1 for generated gds using the same mock PDK?

[krzhu]

https://github.com/magical-eda/MAGICAL/blob/199ab0719f85f74c79bf85a556118b132988a5fe/flow/python/Params.py#L33-L40

[0, 0.1] means default using 0.1um wire width

[120, 0.2] means if net HPWL > 120nm, use 0.2 um width.

You can add more as well.

[AmrMohamedRashed]

@krzhu

1. I tried to change the default value from 0.1 to 0.2 an error occurred and the run fails.
2. How can I change the Via width and space?
3. Whenever I change number of transistor multipliers in .sp file the generated layout is the same which mean the multiplier parameter in .sp file has no effect on generated GDS.
4. what does this mean in MAGICAL/examples/mockPDK/mock.lef VIA VIA12_1C DEFAULT LAYER M1 ; RECT -0.065000 -0.035000 0.065000 0.035000 ; LAYER VIA1 ; RECT -0.035000 -0.035000 0.035000 0.035000 ; LAYER M2 ; RECT -0.035000 -0.065000 0.035000 0.065000 ; END VIA12_1C

[krzhu]

1. It's hard to say whether details.
2. See comments on 4.
3. I am not very knowledgeable about the device generation parts. I guess the current status just ignore it? You can use two parallel identical transistors or change the nf in the netlist to get an equivalence?
4. It's about the VIAs to be used. Each VIA has three layers: two metal layers and one VIA layer. But actually if I remember correctly, we are just used the VIA syntax for reference. In the real layout implementation, we rely on the VIARULE key words later in the file. The router will read the VIARULE blocks and generate a branches of VIA templates. The syntax for VIARULE is a little difficult to explain in one or two sentences. You can refer to the LEF language reference, e.g. https://www.ispd.cc/contests/18/lefdefref.pdf.