Compatibility with BlackIce board?

[sunnystormy]

I'm stoked you're using the open source Verilog toolchain and wanted to see how much effort it would take to create a BlackIce board compatibility profile?

https://www.tindie.com/products/Folknology/blackice-ii/

Please let me know! Thank you.

[maikmerten]

Hi, this should be easily doable. The current SoC (CPU, UART, SPI-Port, LED-Blinkenlights, Timer, boot-ROM and Block-RAM) consume less than 1700 logic cells. The system would thus fit easily into the iCE40 of the BlackIce II board.

The steps necessary would be:

• copy the hx8k-breakout board-specific files (top.v and the pin definitions). The pin definitions need to be adapted for sure, the top.v may fit directly.
• slightly adapt the Makefile

I don't have a BlackIce II, though, to do the port myself.

[sunnystormy]

@maikmerten Thank you for this! Let me look into things, then, and try to figure it out. :)

[maikmerten]

Some hints that may ease porting:

• the boot ROM of the SoC (software/asm/bootrom.s) waits for 500 ms for commands received via UART for software upload. If no commands are received, it tries to load from a SPI Flash/EEPROM device (if one is attached - this is optional). To upload software, I've written software/spu32-serial-bootloader - that one is written in Java (yeah, sorry) and can be compiled with maven (I can also provide a binary if you don't happen to have a JDK around).

• the serial bootloader thingie uses the RTS signal line to reset the system, so the bootloader is made ready to receive commands. I haven't yet figured out how/if this line is connected on the BlackIce II, you may want to consult someone in the know.

• in the loplevel (top.v) you need to specify the clock frequency of the SoC with the localparam CLOCKFREQ. For the HX8K demo board, this is 42 MHz (normal operation) and 5.25 MHz (slow clock, so my cheap logic analyzer can keep up). If you end up using a different frequency, you need to adjust these - otherwise the UART will create the wrong baud rate and the timer will be off as well. The design can usually be clocked safely up to around 50 MHz. Perhaps you can just use the 100 MHz clock signal on the board and use the PLL to divide it down.

• the Makefiles assume that you have a RV32-toolchain installed (compiler, assembler etc.). I'm using the instructions over at https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain (clone picorv32, then do a "make -j$(nproc) build-riscv32i-tools"). Building the toolchain can take a while, be patient.

[sunnystormy]

Just found out about the "Copperboard" here. I think you already have a compatibility file for the HX8K?

https://blog.hackster.io/alchitry-drops-a-pair-of-fpga-boards-and-add-ons-for-new-kickstarter-campaign-650d7dc1ca80

[maikmerten]

Actually, the "compatibility file" is not about HX8K or HX4K, it's about board layout (which pins are connected to which other components on the board). Porting to the "Copperboard" should not be much different to porting to the BlackIce board.

[sunnystormy]

Thanks for the help, I'll start digging around. Cheers!