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Common stuff almost everything else depends on
http://www.makestuff.eu/wordpress/?page_id=1489
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Failed make deps #5

Closed giovannig88 closed 12 years ago

giovannig88 commented 12 years ago

I obtained:

testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 5 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 testCsvf.cpp:36: error: Failure in FPGALink_testRoundTrip: fStatus == FL_SUCCESS testCsvf.cpp:37: error: Failure in FPGALink_testRoundTrip: Expected 4 but was 0 FAILURE: 1 out of 6 tests failed (56 failures). Test time: 0.09 seconds. make[2]: *\ [dbg] Errore 56

Any help?

makestuff commented 12 years ago

There are various files listed in the testCsvf.cpp test, from lines 77 to 104:

https://github.com/makestuff/libfpgalink/blob/master/tests-unit/testCsvf.cpp#L77

Do they exist?

giovannig88 commented 12 years ago

No! The folder /makestuff/libs/libfpgalink/gen_xsvf is empty!

makestuff commented 12 years ago

So what happens if you run rm -rf gen_csvf && make gen_csvf from within makestuff/libs/libfpgalink?

What platform are you using?

Out of interest, why are you building FPGALink from source? Does the binary distribution not meet your needs for some reason? If you want to help with the development of FPGALink we should discuss it offline.

I have just built everything from the current state in GitHub, on an x86_64 Linux machine. Here's what I did:

http://www.swaton.ukfsn.org/temp/build.txt

One thing which is not listed in the prerequisites in the README is the new requirement for Altera Quartus to be installed.

Depending on what you're trying to achieve with building from source, those tests which are failing can probably be ignored; they only verify that the SVF/XSVF/CSVF conversions work OK. And since by building from source myself I have verified that they do work OK, there's no need for you to re-test it.

giovannig88 commented 12 years ago

My platform is an i686. I think the problem it's Altera Quartus is non installed on my pc. Anyway i'm interested to help with the development of this really nice project but i'm busy at all in this period but after the summer we should discuss about that. Thank you!

makestuff commented 12 years ago

Well, I doubt it's Quartus you're missing, because the Altera build comes after the Xilinx build, and none of the files in gen_xsvf come from Quartus. What happens if you run rm -rf gen_csvf && make gen_csvf from within the libfpgalink directory?

giovannig88 commented 12 years ago

Solved!I had a problem with ISE installation. Now i reinstalled ISE and installed Quartus and everything is ok. Now when i try to use the example ex_cksum with a Digilen Nexys 2 when i try to write something i obtain:

Entering CommFPGA command-line mode:

w1 12 flWriteChannel(): flWrite(): usb_bulk_write() failed returnCode -110: No error

The same problem occurs with binaries.

makestuff commented 12 years ago

This is off-topic. Please post your question to the FPGALink mailing list. Please include exactly what you typed on the command-line and what the response was. Also mention whether your Nexys2 is a 500K or 1200K edition, and the position of the power jumper.