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mamreza / pipelined-mips-cpu

Automatically exported from code.google.com/p/pipelined-mips-cpu
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Cannot Synthesize #2

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago 
I imported the src into a new Xilinx ISE project. Syntax is perfect but whan I 
try to Synthesize every component inside the top module (pipelined_cpu) recive 
a warning saying that is unconnected so the final TLC schematic is the 
pipelined_cpu block with the 2 inputs but is not expandable since there's 
nothing inside it!

Suggestions?

Original issue reported on code.google.com by netca...@gmail.com on 8 Sep 2012 at 10:50