Hello,
I am trying to create the lockin+pid project in vivado. But when generating the project I get the following errors:
-[Common 17-55] 'set_property' expects at least one object. ["/rp_lock-in_pid_h-master/lock_in+pid_harmonic/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc":131]
-[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_clocks dac_clk_out]'. ["/rp_lock-in_pid_h-master/lock_in+pid_harmonic/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc":221]
-[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
To generate the script I use vivado 2015.2 on linux computer.
I am a beginner in the subject and I do not understand what is going wrong.
Hello, I am trying to create the lockin+pid project in vivado. But when generating the project I get the following errors:
-[Common 17-55] 'set_property' expects at least one object. ["/rp_lock-in_pid_h-master/lock_in+pid_harmonic/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc":131] -[Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-to [get_clocks dac_clk_out]'. ["/rp_lock-in_pid_h-master/lock_in+pid_harmonic/fpga/project/redpitaya.srcs/constrs_1/imports/sdc/red_pitaya.xdc":221] -[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
To generate the script I use vivado 2015.2 on linux computer.
I am a beginner in the subject and I do not understand what is going wrong.