marekjm / viuavm

Parallel virtual machine designed to reliably run massively concurrent programs
https://viuavm.org/
GNU General Public License v3.0
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Amend VEC instruction #148

Closed marekjm closed 8 years ago

marekjm commented 8 years ago

The vec instruction currently creates a vector inside a register. This issue proposes to extend vec instruction's functionality to include packing, i.e. wrapping objects in vectors.

Example:

strstore 1 "answer to life"
istore 2 42

; pack two objects starting from register 1
vec 3 1 2

The new syntax would be vec <register-index> <start-pack-register-index> <pack-length>.