Open ddurieux opened 5 months ago
with dmidecode -qt cache, I have multiple cache items:
Cache Information Socket Designation: L1 - Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 384 kB Maximum Size: 384 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 8-way Set-associative Cache Information Socket Designation: L2 - Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 3 MB Maximum Size: 3 MB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 8-way Set-associative Cache Information Socket Designation: L3 - Cache Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Write Back Location: Internal Installed Size: 16 MB Maximum Size: 16 MB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 1 ns Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 16-way Set-associative
When I use indent_to_json, I have only the last item (the L3 - Cache).
indent_to_json
L3 - Cache
it's a problem (will do the same when have 2 processors, memories...)
Can do make patch for this case?
I found a workaround, it's a little more complex but will works, when read file / output, split by \n\n to separe items
\n\n
with dmidecode -qt cache, I have multiple cache items:
When I use
indent_to_json
, I have only the last item (theL3 - Cache
).it's a problem (will do the same when have 2 processors, memories...)
Can do make patch for this case?