Ignore paths which use shared clock lines.

[eatnumber1]

Quartus calculates fmax (the theoretical maximum clock rate) based on the entirety of the logic between registers. In the case of the pclk_* lines, this includes some invalid paths which cross between the 3x <-> 2x and 5x <-> 4x clock domains. This is because these clocks share output pins from the PLL, but the PLL is configured to output only one of these clocks at a time, and the correct output from the logic is selected via a multiplexer. Therefore these paths cannot co-occur.

This has the effect of increasing the calculated fmax of these paths to:

pclk_3x: 107.98 MHz -> 132.52 MHz pclk_5x: 162.23 MHz -> 170.33 MHz

[eatnumber1]

Marqs, just so you know I have a series of changes working towards the goal of getting 480p line3x working for the PSP. I'm breaking them out into separate PRs which make some sense to be merged on their own, and I'll also probably have a few questions as I go. Please let me know if you want me to go about this a different way.