Open CSC-Olivier opened 4 years ago
I can reduce power consumption by reducing the core CPU clock. At 8MHz, the SAMD21E17 consume only 2.2mA. But the problem remains, according to the datasheet, we should get 3mA at 48MHz. Is there some initialization in the core that can explain why the consumption is 3 times higher than it should?
Problem: The SAMD21E17A chip uses 8mA in active mode (internal oscillator) and 9mA in active mode (with an external 32kHz crystal) The datasheet (table 37-8 page 988) state the consumption in active should be around 3mA
How to reproduce the problem: Hardware setup: bare chip with 0.1uF bypass cap on VDDIN and VDDANA connected to VCC. 0.1uF cap between VDDCORE and GND. VDDIN and VDDANA are at VCC=3V
Software: Blank sketch compiled using this core uploded with SWD using a J-Link (no bootloader). BOD33 fuse disabled USB disabled in the core menu options