Closed BigEd closed 8 years ago
I think only the shift/rotate instructions have this optimisation - INC/DEC have the same timings as the NMOS 6502. This is a different problem of course to the other Master timing issues!
On 18 Jul 2016 9:31 am, "BigEd" notifications@github.com wrote:
The 65C02 (and presumably 65C102) improved some cycle timings. See http://6502.org/tutorials/65c02opcodes.html
The following test demonstrates that a real Master differs from JSBeeb's Master emulation: 10 P%=&100 20 [NOP 30 SEI:LDA#&20:STA&FE44:STA&FE45 40 LDX#0 50 INC&1FF,X:DEC&1FF,X 60 INC&1FF,X:DEC&1FF,X 70 ROL&1FF,X:ROR&1FF,X 80 ROL&1FF,X:ROR&1FF,X 90 INX 100 INC&1FF,X:DEC&1FF,X 110 INC&1FF,X:DEC&1FF,X 120 ROL&1FF,X:ROR&1FF,X 130 ROL&1FF,X:ROR&1FF,X 140 LDA&FE44:STA&100 150 CLI:RTS 160 ] 170 CALL&101 180 P.~?&100
On JSBeeb, we get E4 in both B mode and Master 128 mode. On a real B we get E4 but on a real Master we get E6
So in this case JSBeeb's Master seems to be running slow.
The test measures the composite of INC, DEC, ROL and ROR in both page-crossing and non-page-crossing cases. I haven't tried to narrow the results down, or to include ASL and LSR which should also be checked.
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Indeed, and I was wondering if JSBeeb had adjusted all 6 RMW instead of just 4. But it seems JSBeeb hasn't adjusted any of them!
Here's a more fine-grained version of the test:
10 P%=&100 20 [ 30 NOP:NOP:NOP:NOP 40 NOP:NOP:NOP:NOP 50 SEI:LDA#&20:STA&FE44:STA&FE45 60 LDX#&FF 70 INC&41FF,X:INC&41FF,X 80 LDA&FE44:STA&100 90 DEC&41FF,X:DEC&41FF,X 100 LDA&FE44:STA&101 110 ROL&41FF,X:ROL&41FF,X 120 LDA&FE44:STA&102 130 ROR&41FF,X:ROR&41FF,X 140 LDA&FE44:STA&103 150 INX 160 INC&41FF,X:INC&41FF,X 170 LDA&FE44:STA&104 180 DEC&41FF,X:DEC&41FF,X 190 LDA&FE44:STA&105 200 ROL&41FF,X:ROL&41FF,X 210 LDA&FE44:STA&106 220 ROR&41FF,X:ROR&41FF,X 230 LDA&FE44:STA&107 240 CLI:RTS 250 ] 260 CALL&101 270 P.~!&100,~!&104
On real Master: F2FE0A16 C3CED9E5
On JSBeeb's Master: F2FE0A16 C1CDD9E5
On JSBeeb's Model B F2FE0A16 C1CDD9E5
Test only the non-page crossing case, but all RMW instructions:
10 P%=&100 20 [ 30 NOP:NOP:NOP:NOP 40 NOP:NOP:NOP:NOP 50 SEI:LDA#&20:STA&FE44:STA&FE45 60 LDX#0 70 INC&41FF,X:INC&41FF,X 80 LDA&FE44:STA&100 90 DEC&41FF,X:DEC&41FF,X 100 LDA&FE44:STA&101 110 ROL&41FF,X:ROL&41FF,X 120 LDA&FE44:STA&102 130 ROR&41FF,X:ROR&41FF,X 140 LDA&FE44:STA&103 150 LSR&41FF,X:LSR&41FF,X 160 LDA&FE44:STA&104 170 ASL&41FF,X:ASL&41FF,X 180 LDA&FE44:STA&105 190 CLI:RTS 200 ] 210 CALL&101 220 P.~!&100,~!&104
Real Master: F4FF0A16 EAEADEE9
JSBeeb Model B and also Master: F2FE0A16 EAEADAE6
Thanks for your help with this guys: I combined the tests @BigEd posted into one and then ensured that it failed as before, then fixed the opcodes. Now all passes: yay! Decimal mode is still wrong, but I'll have to look into that another time...
The 65C02 (and presumably 65C102) improved some cycle timings. See http://6502.org/tutorials/65c02opcodes.html
The following test demonstrates that a real Master differs from JSBeeb's Master emulation: 10 P%=&100 20 [NOP 30 SEI:LDA#&20:STA&FE44:STA&FE45 40 LDX#0 50 INC&1FF,X:DEC&1FF,X 60 INC&1FF,X:DEC&1FF,X 70 ROL&1FF,X:ROR&1FF,X 80 ROL&1FF,X:ROR&1FF,X 90 INX 100 INC&1FF,X:DEC&1FF,X 110 INC&1FF,X:DEC&1FF,X 120 ROL&1FF,X:ROR&1FF,X 130 ROL&1FF,X:ROR&1FF,X 140 LDA&FE44:STA&100 150 CLI:RTS 160 ] 170 CALL&101 180 P.~?&100
On JSBeeb, we get E4 in both B mode and Master 128 mode. On a real B we get E4 but on a real Master we get E6
So in this case JSBeeb's Master seems to be running slow.
The test measures the composite of INC, DEC, ROL and ROR in both page-crossing and non-page-crossing cases. I haven't tried to narrow the results down, or to include ASL and LSR which should also be checked.