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matthewlai / JLCKicadTools

Tool for using JLCPCB assembly service with KiCad
GNU General Public License v3.0
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ESP32-WROOM-32 Placement issue #59

Closed mholiv closed 3 years ago

mholiv commented 3 years ago

Hello! Thanks for your help. I found this issue that may affect a class of ICs, but I only verified it with the one IC that I noticed it with initially.

Overview

I have a PCB that involves a ESP32-WROOM-32 SoC.

I noticed that in the jlcpcb rendering that the ESP32-WROOM-32 seems to be placed lower then it ought to. (see image) jlcpcb seems to correct this manually, but ideally this should not be needed.

esp32-bug

Reproduction

I have not not rigorously tested this issue but I get it by:

Use JLCKicadTools version with commit hash https://github.com/matthewlai/JLCKicadTools/commit/62cd76ccb93123548396ae8329195747ca64e8cd

  1. Include a ESP32-WROOM-32 SoC in your Eeschema with RF_Module:ESP32-WROOM-32 symbol and the RF_Module:ESP32-WROOM-32 footprint.
  2. Generate BoM/Netlist
  3. In Pcbnew import that netlist and position the ESP32-WROOM-32
  4. Generate a .pos footprint file
  5. Generate drill/plot files
  6. Enter working dir and run jlc-kicad-tools -n my_project -v --warn-no-lcsc-partnumber . -o g
  7. Upload files to to jlcpcb
  8. Upload generated bom and cpl files.
  9. View misplaced ESP32-WROOM-32
matthewlai commented 3 years ago

Thanks for the report. I had noticed that as well.

There is no (easy) way for us to fix it unfortunately. We do not modify component positions from KiCad. It looks like maybe KiCad's footprint uses the centre point of all the pads as origin, and JLC uses the centre of the entire footprint. We have no way of knowing JLC's footprint dimensions, and these are all irregularly shaped components. This affects connectors where the centre of the footprints doesn't match the centre of the pads, too, and I've had a few boards made and they were all corrected by JLC.