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matthiasschweikart / HDL-FSM-Editor

A tool for modeling FSMs by VHDL or Verilog
http://www.hdl-fsm-editor.de/
MIT License
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Add Transition Verifications before Generating HDL #1

Closed StefanBalt closed 1 month ago

StefanBalt commented 1 month ago

I am not sure how, but we did manage to break a transition and it does not have a destination anymore. Here is the stripped-down FSM: transition_not_connected.hfe.json

This can potentially cause critical failures that are not visible in the diagram.

I noticed there is already a verification for a reset condition. In a similar way it would be nice to have a check whether all transitions have a valid source and destination.

matthiasschweikart commented 1 month ago

The broken transition has a destination in the "graphical" information of the database (transition_not_connected.hfe.json). But the transition does not have a destination in the "logical" part of the database. This situation was probably caused by a bug in HDL-FSM-Editor, for which I will look for. I will also add a plausibility check for the database which will be called when HDL is generated. As I will be at vacation for a week now, expect a new version of the tool in about 2 weeks.

matthiasschweikart commented 1 month ago

I did not find the reason why the database got corrupted. In version 4.1 of HDL-FSM-Editor now a plausibility check is executed, when HDL is generated. This check identifies problems like present in transition_not_connected.hfe.json and gives a hint to the user how to fix the problem.